Track-and-Hold Circuit Switching for Fast Signal Isolation
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Solution Overview
Problem
Traditional track and hold circuits suffer from strong sample-and-hold coupling and reduced switching speed due to the drive transistor operating in a linear region during the hold phase, leading to undesirable signal isolation and reduced sampling frequency.
Innovation Solution
A track and hold circuit design featuring an input buffer amplifier, a unit gain amplifier module, a sampling switch, a drive triode, and a sampling capacitor, where the sampling switch is connected to the emitter of the drive triode during the track phase and disconnected during the hold phase, with an overdrive protection module to prevent deep saturation and multi-polar isolation to reduce interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the drive transistor operates in linear region during hold phase, then the circuit structure is simple, but the switching speed is reduced
Solution Approach 1:
The patent applies dynamic operation by switching the drive transistor between saturation region during track phase and cutoff region during hold phase, rather than operating continuously in linear region. This dynamic switching state changes resolve the contradiction by achieving high-speed switching while maintaining circuit simplicity through controlled state transitions.
Solution Approach 2:
The patent changes the operating parameters of the drive transistor by controlling its base voltage to transition between saturation and cutoff regions. During track phase, the transistor is driven into saturation for fast charging; during hold phase, it is cut off for complete isolation. This parameter change resolves the contradiction between simple structure and high switching speed.
2Device complexity
If the drive transistor operates in linear region during hold phase, then the circuit design is straightforward, but the signal isolation between sample and hold is poor
Solution Approach 1:
The patent extracts the drive transistor from the linear operation state during hold phase and transitions it to cutoff region, effectively removing the coupling path between sample and hold signals. This extraction of the harmful coupling effect while maintaining straightforward circuit design resolves the contradiction.
Solution Approach 2:
Instead of using linear region operation to maintain signal continuity, the patent inverts the approach by using cutoff region operation during hold phase to achieve complete isolation. This inversion of the operational state resolves the contradiction between simple design and poor signal isolation.
3Ease of operation
If the sampling switch is connected to emitter during track phase, then the charging function is achieved, but the switching speed is reduced due to linear region operation
Solution Approach 1:
The patent dynamically adjusts the drive transistor's operating region based on the phase: saturation during track phase for fast charging while maintaining connection, and cutoff during hold phase for complete disconnection and high switching speed. This dynamic adjustment resolves the contradiction between charging function and switching speed.
4Power
If the drive transistor is used to charge the sampling capacitor, then the charging capability is provided, but the sample-and-hold coupling is strong
Solution Approach 1:
The patent employs periodic action by alternating the drive transistor's state between track phase (charging) and hold phase (isolation). During track phase, the transistor charges the capacitor; during hold phase, it cuts off to eliminate coupling. This periodic switching resolves the contradiction between charging capability and sample-and-hold coupling.
Data Source
AI summary
A track and hold circuit comprises an input buffer amplifier, a unit gain amplifier module, a sampling switch, a drive triode and a sampling capacitor. The input buffer amplifier receives an input signal. In a track phase, the sampling switch is electrically connected to an emitter electrode of the drive triode; the input signal charges the sampling capacitor after being buffered by the input buffer amplifier, amplified without distortion by the unit gain amplifier module and driven by the drive triode. In a hold phase, the sampling switch is electrically connected to a base electrode of the drive triode; the base voltage of the drive triode is pulled down until the drive triode is cut off; electrical charges on the sampling capacitor are thereby held, causing the signal to be held on the sampling capacitor.