Tracking Bit Line Timing Circuit for Low-VDD SRAM Write Assist
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Solution Overview
Problem
Existing SRAM bit cells face challenges in maintaining low leakage current and reducing the incidence of read flips while ensuring successful write operations, particularly when the VDD voltage is near Vccmin.
Innovation Solution
The implementation of a memory device with a write assist circuit that temporarily pulls the bit line voltage to a transient negative voltage level during write operations, ensuring data can be written successfully even at lower VDD levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the VDD voltage is reduced to near Vccmin, then leakage current is reduced and read flips are minimized, but write operation success probability deteriorates
Solution Approach 1:
The write assist circuit performs preliminary action by pre-charging the bit line to a higher voltage level (e.g., VDD + Voverdrive) before the actual write operation. This preliminary voltage preparation ensures that when the write operation occurs, there is sufficient voltage differential to overcome the weakened write capability at low VDD levels, thus maintaining write reliability while allowing VDD to be operated near Vccmin for reduced leakage.
Solution Approach 2:
The invention dynamically changes the bit line voltage parameter during the write operation. The write assist circuit temporarily boosts the bit line voltage to a higher level (VDD + Voverdrive) during the write window, then returns it to normal levels. This parameter change creates the necessary voltage conditions for successful writes at low VDD while maintaining low leakage current when VDD is near Vccmin.
2Reliability
If the VDD voltage is increased, then write operation success probability is improved, but leakage current increases
Solution Approach 1:
Instead of continuously maintaining high VDD to ensure write success, the write assist circuit performs preliminary voltage preparation only when needed during write operations. The bit line is pre-charged to VDD + Voverdrive temporarily, providing sufficient write capability without requiring continuously elevated VDD, thus avoiding increased leakage current while maintaining write reliability.
Solution Approach 2:
The write assist circuit operates periodically only during write operations rather than continuously. The bit line voltage is boosted to VDD + Voverdrive temporarily during the write window and then returns to normal levels. This periodic action provides write assistance only when necessary, preventing continuous leakage current increase that would result from maintaining high VDD throughout operation.
3Loss of energy
If a write assist circuit is implemented to enable low VDD operation, then leakage current is reduced, but device complexity increases
Solution Approach 1:
The write assist circuit is designed with multi-functionality to justify its added complexity. It serves multiple purposes: pre-charging the bit line to VDD + Voverdrive, providing voltage compensation during write operations, and enabling low VDD operation for leakage reduction. By consolidating these functions into a single circuit block, the complexity increase is minimized while achieving the goal of reduced leakage current through low VDD operation.
Data Source
AI summary
A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.