Tracking Word Line Timing for Negative Bit Line SRAM Writes
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Solution Overview
Problem
In SRAM bit cells, reducing the VDD voltage to minimize leakage current increases the probability of write failures due to insufficient voltage difference for overriding stored data, limiting the lower bound of VDD by the write operation.
Innovation Solution
A write assist circuit temporarily pulls the bit line voltage to a transient negative voltage level during write operations, ensuring data can be successfully written by adjusting the timing of the negative bit line trigger signal using a timing control circuit that adapts to the memory array's parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the VDD voltage is reduced to minimize leakage current, then power consumption is reduced, but the probability of write failures increases due to insufficient voltage difference
Solution Approach 1:
The write assist circuit performs preliminary action by pre-charging the bit line to a higher voltage level before the write operation begins. This preliminary voltage preparation ensures that when the write operation occurs at reduced VDD levels, there is sufficient voltage difference to successfully override the stored data in the SRAM cell, thereby preventing write failures while maintaining low power operation.
Solution Approach 2:
The write assist circuit acts as an intermediary between the write driver and the SRAM cell. It introduces an additional voltage boosting mechanism that mediates the voltage difference requirement during write operations. The write assist circuit temporarily enhances the bit line voltage beyond what the reduced VDD can provide, enabling successful writes without requiring the entire system to operate at high voltage, thus maintaining low leakage current while ensuring write reliability.
2Reliability
If the VDD voltage is increased to improve write operation probability, then write success rate improves, but leakage current increases
Solution Approach 1:
The write assist circuit performs preliminary voltage preparation by pre-charging the bit line to a high voltage level before the actual write operation. This allows the main VDD voltage to remain at low levels for minimizing leakage, while the bit line temporarily receives the additional voltage boost only when needed for the write operation, thus achieving high write success rate without continuous high power consumption.
Solution Approach 2:
The write assist circuit operates periodically only during write operations rather than continuously. The voltage boosting is applied transiently when a write operation is detected and then discontinued, allowing the system to maintain low VDD levels for normal operation (minimizing leakage) while providing high voltage support only when required for write operations (ensuring write success).
Data Source
AI summary
A circuit includes a tracking word line, a power switch, a tracking bit line, a sense circuit. The power switch is coupled between the tracking word line and a first node. The power switch is configured to discharge a voltage level on the first node in response to a clock pulse signal transmitted through the tracking word line to the power switch. The tracking bit line is coupled between the first node and a plurality of tracking cells in a memory array. The sense circuit is coupled between the first node and a second node. The sense circuit is configured to generate a negative bit line enable signal in response to that the voltage level on the first node is below a threshold voltage value of the sense circuit.