High-Frequency Trading Inference Pipeline for Low-Latency Prediction

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Solution Overview

Problem

High frequency trading using machine learning models faces challenges with latency issues due to complex computations on large data volumes, leading to inaccuracies in prediction, and existing processors lack sufficient storage and processing resources, resulting in time gaps where prediction data is outdated by the time it is used.

Innovation Solution

A method and system that utilize a dedicated accelerator (NPU ASIC) for machine learning models, coupled with flexible pre-/post-processing via FPGA, to minimize latency by selecting optimal batch sizes and calculating latency for each future time point, ensuring accurate and timely prediction data generation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If machine learning models are used to analyze large amounts of market data for high frequency trading, then prediction accuracy is improved, but processing time increases causing latency

Engineering Contradiction:
Improveprediction accuracyVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent segments the processing workflow into distinct stages: data preprocessing, machine learning inference, and order generation. By using separate processors for each stage (FPGA for preprocessing, NPU for ML inference, CPU for order generation), the system can process multiple batches in parallel, reducing overall latency while maintaining prediction accuracy through specialized hardware acceleration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary actions by pre-processing market data into feature maps before ML inference, and by predicting latency for different batch sizes in advance. This allows the system to select optimal batch sizes that balance prediction accuracy with processing time constraints, ensuring predictions are generated before the target time point.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If larger batch sizes are used for machine learning processing, then processing efficiency is improved, but latency increases causing prediction data to become outdated

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidprediction timeliness
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The system dynamically adjusts batch sizes based on predicted latency and target time points. Instead of using a fixed batch size, the patent calculates latency for different batch sizes and selects the optimal size that ensures predictions are completed before the target time point, thereby maintaining both processing efficiency and prediction timeliness.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the batch size parameter dynamically based on market conditions and processing requirements. By predicting latency for different batch sizes and selecting the optimal one, the system adapts the processing parameters to balance efficiency and timeliness, preventing prediction data from becoming outdated.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If existing processors are used for machine learning operations, then device complexity is reduced, but storage and processing resources are insufficient

Engineering Contradiction:
Improvesystem simplicityVSAvoidstorage and processing resources
Core Design Contradiction:
Device complexityVSQuantity of substance

Solution Approach 1:

The patent introduces an intermediary NPU ASIC specifically designed for machine learning operations, which acts as a bridge between the existing CPU/FPGA infrastructure and the ML models. This intermediary provides the necessary storage and processing resources for ML operations without completely replacing the existing processor architecture, thus managing complexity while enhancing capabilities.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system uses a composite processing architecture combining FPGA, NPU ASIC, and CPU, where each component contributes its strengths. The FPGA handles data preprocessing, the NPU ASIC provides specialized ML inference with sufficient storage and processing resources, and the CPU manages order generation. This composite approach provides the necessary resources without excessive complexity.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS20250348932A1Method and system for high frequency trading
Publication Date: 2025.11.13 REBELLIONS INC
  • US20250348932A1 patent drawing
  • US20250348932A1 patent drawing
  • US20250348932A1 patent drawing

AI summary

A method for high frequency trading is provided, which is performed by one or more processors, and includes generating input data based on market data for a target item, generating prediction data for the target item for each of a plurality of future time points by inputting the generated input data to a machine learning model, and generating order data for the target item based on the generated prediction data.