Parallel Trailing Zero Counter Using OR Reduction Logic
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Solution Overview
Problem
Existing zero counters for binary numbers are inefficient in calculating the number of trailing or leading zeros, particularly in applications like subtraction and floating-point normalization, as they often require sequential processing of bits and do not adapt well to the timing profiles of preceding logic blocks.
Innovation Solution
A trailing/leading zero counter design utilizing a plurality of hardware logic blocks that recursively split the input string into non-overlapping sections, allowing parallel processing and incorporating OR reduction stages to combine adjacent bits, thereby optimizing the calculation of zero counts and matching the timing profile of preceding logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If sequential processing of bits is used in existing zero counters, then the device complexity is reduced, but the processing speed and productivity deteriorate
Solution Approach 1:
The patent divides the input binary string into multiple non-overlapping sections and uses separate hardware logic blocks to process each section in parallel. Each hardware logic block contains section hardware logic that processes a specific section independently, and combining logic that merges the results. This segmentation enables simultaneous processing of multiple bit sections, dramatically improving processing speed while maintaining manageable device complexity through modular architecture.
2Productivity
If parallel processing is implemented to improve processing speed, then the productivity increases, but the device complexity increases
Solution Approach 1:
The patent implements a hierarchical structure where hardware logic blocks are nested within arrays, and combining logic is nested within each hardware logic block to merge section results. The OR reduction stages are nested within the section hardware logic. This nested organization allows parallel processing at multiple levels while reusing logic structures, thereby improving processing speed without proportionally increasing device complexity.
3Adaptability or versatility
If OR reduction stages are added to match timing profiles, then the adaptability improves, but the device complexity increases
Solution Approach 1:
The patent makes the number of OR reduction stages dynamic by configuring each hardware logic block to have a specific number of OR reduction stages based on the desired timing profile. This allows the system to adapt to different timing requirements of preceding logic blocks by adjusting the depth of OR reduction in each hardware logic block, providing timing flexibility without requiring complete redesign for different applications.
4Productivity
If more hardware logic blocks are used to improve processing parallelism, then the productivity increases, but the loss of time in coordinating the blocks increases
Solution Approach 1:
The patent performs preliminary actions by pre-configuring the number of OR reduction stages in each hardware logic block to match the timing profile of preceding logic. This preliminary timing alignment ensures that results from different parallel hardware logic blocks become available simultaneously, eliminating coordination delays and maximizing the efficiency of parallel processing without time loss in synchronization.
Data Source
AI summary
A trailing/leading zero counter is described which comprises a plurality of hardware logic blocks, each of which calculates one bit of the output value (i.e. the number of trailing/leading zeros depending on whether it is a trailing/leading zero counter). Each hardware logic block comprises two blocks of section hardware logic which each receive a section of an input string and generate one or two outputs from this section of bits. Combining logic then combines the outputs of the section hardware logic to generate the bit of the output value. For hardware logic blocks which calculate bits other than the least significant bit of the output, the hardware logic blocks also comprise one or more OR reduction stages which reduces the length of the input string by pairwise combining of bits using OR gates before the resultant string is divided into two sections and input to the section hardware logic.