Trans-threshold Correlation for SoC Subthreshold Testing
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Solution Overview
Problem
Subthreshold system-on-a-chip (SoCs) face significant challenges in testing due to increased test times and costs, as lowering operating voltage to reduce power consumption results in lower operating frequency and longer at-speed testing times, making commercialization less feasible.
Innovation Solution
The method involves establishing trans-threshold correlations between normal and subthreshold operating voltages to predict test times and power values at low voltages, allowing for faster identification of functional failures and chip binning, without requiring additional on-chip circuits, and can be applied to various types of circuits, including digital, memory, and analog/mixed signal circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If operating voltage is lowered to reduce power consumption, then power consumption decreases, but testing time increases significantly
Solution Approach 1:
The patent performs preliminary characterization of delay metrics at both subthreshold and normal operating voltages to establish correlation models before actual testing. This preliminary action enables prediction of subthreshold test times based on normal voltage test results, avoiding the need to perform actual lengthy subthreshold tests for every chip.
Solution Approach 2:
The patent uses normal operating voltage test results as an intermediary to predict subthreshold operating voltage test outcomes. By establishing delay metric correlations between the two voltage regimes, the normal voltage tests serve as a mediator that provides information about subthreshold performance without requiring direct subthreshold testing.
2Use of energy by stationary object
If operating voltage is lowered to reduce power consumption, then power consumption decreases, but operating frequency decreases making testing less feasible
Solution Approach 1:
The patent uses normal operating voltage tests as an intermediary to obtain speed-related information without actually operating the chip at subthreshold voltages during testing. The delay metrics measured at normal voltage serve as a proxy for predicting subthreshold speed characteristics.
Solution Approach 2:
The patent changes the operating voltage parameter during testing to normal voltage levels, where the chip operates at higher frequencies, while still obtaining information relevant to subthreshold performance through established correlations between delay metrics at different voltages.
3Productivity
If trans-threshold correlations are established to predict test times, then testing speed increases, but measurement precision requirements increase
Solution Approach 1:
The patent replaces direct subthreshold testing (mechanical/time-consuming process) with correlation-based prediction (computational approach). By substituting the physical testing process with a mathematical model based on delay metric correlations, testing speed increases while maintaining acceptable precision through statistical characterization.
Data Source
AI summary
A method for testing system-on-a-chip (SoC) for faults at subthreshold or substantially at threshold operating voltages includes the steps of testing the SoC for fault at a favorable operating voltage, the testing including measuring a metric characterizing the fault at the favorable operating voltage to obtain a first metric value; and retesting the SoC for the fault at a first operating voltage upon the first metric value at the favorable operating voltage being correlated, according to a metric correlation establishing a correlation relationship between the favorable operating voltage and the first operating voltage, to a second metric value at the first operating voltage within a predictive interval of the metric correlation.