Transaction Attribute Storage Circuitry for Latency Reduction

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Solution Overview

Problem

Existing data processing circuitry lacks an efficient mechanism to associate and reuse resolutions for data handling transactions, leading to inefficiencies in handling transactions like address translation, particularly due to high latency in accessing translation information from memory.

Innovation Solution

The circuitry includes attribute storage, comparator, and control circuitry to identify and associate data handling transactions that can be resolved using existing transaction attributes, forming a set of associated transactions, and providing the resolution to the transaction source, thereby reducing redundant requests and improving efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If address translation transactions are handled by accessing translation information from memory, then translation accuracy is ensured, but transaction latency increases significantly

Engineering Contradiction:

Improvetranslation accuracyVSAvoidtransaction latency

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent pre-fetches translation information from memory and stores it in buffer circuitry before it is actually needed for transaction resolution. By performing the memory access in advance and caching the translation data locally, the system eliminates the latency penalty during actual translation operations while maintaining accuracy through buffered data.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces buffer circuitry as an intermediary layer between the transaction source and the translation information. This buffer acts as a mediator that holds translation data temporarily, allowing transactions to be resolved quickly by comparing attributes with buffered information rather than directly accessing memory for each transaction.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If translation information is cached in buffer circuitry, then transaction handling speed improves, but circuitry complexity increases

Engineering Contradiction:

Improvetransaction handling speedVSAvoidcircuitry complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the translation information into discrete transaction attribute components that can be independently buffered and compared. By segmenting the translation data into manageable attribute fields, the system can efficiently cache and search specific attributes without requiring complex full-record buffering, thus improving speed while controlling complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent creates simplified copies of translation information in the buffer, storing only the essential transaction attributes needed for comparison rather than complete translation records. This copying approach enables fast transaction resolution through attribute matching while keeping the buffer structure relatively simple and manageable.

Inventive Principle:

Principle #26Copying

3Loss of energy

If multiple transactions are associated and resolved together, then data traffic to memory is reduced, but transaction management complexity increases

Engineering Contradiction:

Improvedata trafficVSAvoidtransaction management

Core Design Contradiction:

Loss of energyVSDevice complexity

Solution Approach 1:

The patent merges multiple related transactions into association groups based on their attribute similarities. By combining transactions that share common translation attributes, the system can resolve them collectively using a single buffered translation entry, thereby reducing redundant memory accesses and data traffic while managing complexity through attribute-based grouping logic.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a universal buffer entry that can serve multiple associated transactions simultaneously. Instead of maintaining separate buffered information for each transaction, a single buffered translation entry can be reused across multiple transactions that share the same attribute characteristics, reducing overall system complexity while minimizing data traffic to memory.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11281403B2Circuitry and method

Publication Date: 2022.03.22 ARM LTD

AI summary

Circuitry comprises attribute storage circuitry having a plurality of entries to hold data defining at least a transaction attribute of one or more respective data handling transactions initiated by transaction source circuitry; comparator circuitry to compare a transaction attribute of a given data handling transaction with data held by the attribute storage circuitry to detect whether the given data handling transaction would be resolved by any data handling transaction for which attribute data is held by a respective entry in the attribute storage circuitry; and control circuitry to associate the given data handling transaction with the respective entry in the attribute storage circuitry to form a set of associated data handling transactions when the comparator circuitry detects that the given data handling transaction would be fulfilled by the data handling transaction for which attribute data is held by the respective entry in the attribute storage circuitry; the control circuitry comprising output circuitry responsive to a resolution of a data handling transaction in the set of associated data handling transactions, to provide that resolution to the transaction source circuitry as a resolution of each of the set of associated transactions.