Transaction-Based Shared Memory Protection for High Availability

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Solution Overview

Problem

In high availability environments, shared memory protection mechanisms face challenges in maintaining memory coherency and ensuring recovery from restart events, particularly when a thread is interrupted during a critical section, as the restarted thread cannot determine the progress of multi-word updates and may leave shared memory in an incoherent state.

Innovation Solution

A transaction-based shared memory protection mechanism is introduced, where operations are saved to a protected memory area and a gate flag indicates successful completion, allowing for 'all or nothing' transactions. This includes lock-based and lock-free/wait-free implementations, using staging areas and descriptors to manage shared memory updates and ensure recovery by analyzing the protected memory and executing operations accordingly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If mutual exclusion mechanisms (semaphores and mutexes) are used to protect shared memory, then concurrency issues are handled, but reliability deteriorates when a process or thread restarts during a critical section

Engineering Contradiction:
Improveconcurrency handlingVSAvoidmemory coherency after restart
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent implements a two-stage critical section mechanism where the first stage prepares a staging area with all necessary operations and validity indicators before the second stage executes them. This preliminary preparation ensures that if a restart occurs during execution, the system can recover by checking the validity indicators and re-executing only the necessary operations, thereby maintaining reliability while preserving concurrency handling capabilities.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The critical section is divided into two distinct stages: a preparation stage where operations are staged in a protected area with validity indicators, and an execution stage where the actual memory operations occur. This segmentation allows the system to track the state of each operation independently, enabling reliable recovery after restarts while maintaining concurrency control through the staged approach.

Inventive Principle:
Principle #1Segmentation

2Reliability

If a thread is interrupted during a critical section, then high availability is improved through restart capability, but manufacturing precision deteriorates as the restarted thread cannot determine the progress of multi-word updates

Engineering Contradiction:
Improverestart capabilityVSAvoidupdate progress tracking
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent uses validity indicators (analogous to color changes or state markers) associated with each staged operation to indicate whether the operation has been successfully executed. These indicators provide a clear, observable state that allows the restarted thread to determine exactly which operations have been completed and which need re-execution, thereby maintaining precise tracking of update progress while enabling restart capability.

Inventive Principle:
Principle #32Color changes

Solution Approach 2:

The system implements feedback through validity indicators that provide information about the execution status of each staged operation. When a thread restarts, it can query these indicators to receive feedback on which operations were successfully completed before the interrupt, allowing the thread to resume execution from the correct point and maintain precise update tracking.

Inventive Principle:
Principle #23Feedback

3Adaptability or versatility

If multi-word updates are performed in shared memory, then functionality is improved, but device complexity increases as the system must track and recover partial updates

Engineering Contradiction:
Improveshared memory functionalityVSAvoidupdate tracking mechanism
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Multi-word updates are segmented into individual operations, each stored in the staging area with its own validity indicator. This segmentation transforms a complex multi-word update tracking problem into a series of simpler, independently trackable operations. The system can track and recover each operation separately, reducing the overall complexity while maintaining full multi-word update functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The staging area acts as an intermediary structure that holds the complete set of operations and their validity indicators before execution. This intermediary mechanism simplifies tracking by providing a centralized, organized representation of all update operations and their states, making the tracking and recovery process more manageable while supporting complex multi-word updates.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8893137B2Transaction-based shared memory protection for high availability environments
Publication Date: 2014.11.18 CISCO TECHNOLOGY INC
  • US8893137B2 patent drawing
  • US8893137B2 patent drawing
  • US8893137B2 patent drawing

AI summary

Various systems and methods for implementing a transaction-based shared memory protection for high availability environments are described herein. A processing thread is executed, with the processing thread configured to access a multi-stage critical section, the multi-stage critical section having a first and second stage, the first stage to store a staging area of a plurality of operations to be executed in the memory shared with at least one other processing thread, and the second stage to execute the operations from the staging area. The thread further configured to determine whether the staging area includes an indication of successfully completing the first stage and execute the operations when there is an indication of successfully completing the first stage.