Transaction Buffer for Flash Memory Data Integrity

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Solution Overview

Problem

Conventional flash memory systems face errors during data commit due to interrupted transactions, leading to partial data storage and corruption, especially when dealing with non-contiguous or larger-than-buffer-size user data.

Innovation Solution

A transaction buffer component temporarily stores user data, and a transaction bit component manages transaction start and end bits to ensure complete data transfer only after the transaction is fully completed, using a controller component to track and resume data transfer if interrupted.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional flash memory systems write data directly to memory locations during transactions, then data transfer speed is improved, but data integrity deteriorates when transactions are interrupted

Engineering Contradiction:
Improvedata transfer speedVSAvoiddata integrity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The system performs preliminary actions by storing transaction data in a dedicated buffer component before actual memory writing occurs. The buffer holds data until the transaction is fully committed, preventing partial writes to memory locations. This preliminary buffering action ensures that even if power is lost during the transfer, the data remains intact in the buffer and can be recovered without corrupting the memory.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A buffer component is introduced as an intermediary between the data source and the flash memory locations. This buffer acts as a mediator that temporarily holds transaction data, allowing the system to complete transactions atomically. The buffer decouples the data transfer process from the actual memory write operation, enabling interruption recovery while maintaining data integrity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If flash memory systems handle non-contiguous or large data sets in multiple writes, then adaptability is improved, but transaction consistency deteriorates

Engineering Contradiction:
Improvehandling non-contiguous dataVSAvoidtransaction consistency
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The system segments the data handling process into distinct phases: data collection in the buffer, transaction commit validation, and memory writing. This segmentation allows non-contiguous data to be collected in the buffer during a single logical transaction, then written to multiple memory locations atomically. The transaction bit component tracks the segmentation and ensures all segments are committed together, maintaining transaction consistency despite the non-contiguous nature of the data.

Inventive Principle:
Principle #1Segmentation

3Reliability

If the system implements transaction buffering and commit validation, then data integrity is improved, but device complexity increases

Engineering Contradiction:
Improvedata integrityVSAvoidsystem structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The buffer component is designed to be self-managing with automatic transaction bit tracking and commit validation. The system monitors its own state through transaction bits that automatically indicate whether data in the buffer is committed or uncommitted. This self-service mechanism reduces the need for external complexity in managing transaction integrity, as the buffer autonomously handles the validation and recovery processes.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8788740B2Data commit on multicycle pass complete without error
Publication Date: 2014.07.22 SPANSION LLC
  • US8788740B2 patent drawing
  • US8788740B2 patent drawing
  • US8788740B2 patent drawing

AI summary

A system and methodology that can prevent errors during data commit on multicycle pass complete associated with a memory is provided. The system employs a transaction buffer component in the memory that receives and temporarily stores information associated with a transaction. A controller component programs subsets of data to respective memory locations once the entire transaction is completed based on the information stored in the transaction buffer component. Thus, if the transaction is interrupted during the transfer of the user data into the buffer, the data stored in the memory is not affected and can still contain the original data when power is regained. If the data transfer between the transaction buffer component and memory array is interrupted, the controller component can complete the transfer from the point of interruption on regaining power and can avoid partial storage of data.