Transaction-Based Clock Gating for Low-Power Logic Pipelines
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Solution Overview
Problem
Current IC design tools are inefficient for asynchronous designs due to their synchronous design methodologies, leading to longer design cycles and increased dynamic power consumption, as they struggle to accommodate on-demand clock generation and propagated clocks effectively.
Innovation Solution
A clock control block (CCB) system that generates clock pulses on demand and propagates clock requests synchronously, reducing unnecessary clocking of pipeline stages and minimizing dynamic power by activating only required flip-flops with transaction-based clocking and multi-cycle clocking techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If synchronous design methodologies are used in IC design tools, then design cycle time is reduced and ease of manufacture is improved, but dynamic power consumption increases due to unnecessary clocking of pipeline stages
Solution Approach 1:
The patent implements dynamic clock gating control where the clock signal is enabled or disabled based on actual transaction activity in the pipeline stages. The clock enable signal dynamically adjusts to match the operational needs of each pipeline stage, allowing the system to maintain synchronous design methodology benefits while reducing power consumption by eliminating clocks to inactive stages.
Solution Approach 2:
The patent applies local clock gating to individual pipeline stages based on their specific operational requirements. Each pipeline stage receives a clock enable signal tailored to its activity level, allowing different parts of the design to have different clocking characteristics - active stages receive continuous clocks while inactive stages receive gated clocks, optimizing power efficiency without compromising overall design productivity.
2Reliability
If more pipeline stages are clocked, then manufacturing precision and reliability are improved, but dynamic power consumption increases
Solution Approach 1:
The clock gating mechanism dynamically enables or disables clock signals to pipeline stages based on real-time transaction activity detection. When a pipeline stage is actively processing data, the clock enable signal is asserted to maintain reliable operation. When the stage is inactive, the clock is gated off to reduce power consumption, thus maintaining reliability only where needed.
Solution Approach 2:
The patent applies clock gating to selectively enable clocks only to the necessary pipeline stages that are currently active, rather than enabling clocks to all pipeline stages unconditionally. This partial action approach ensures that sufficient clocking is provided to maintain reliability for active stages while avoiding excessive clocking to inactive stages, thereby reducing overall dynamic power consumption.
3Use of energy by moving object
If asynchronous design methodologies are used, then dynamic power consumption is reduced, but design cycle time increases due to tool constraints
Solution Approach 1:
The patent segments the clocking control into separate clock gating units for different pipeline stages, each independently controlled by transaction activity detection. This segmentation allows the design to maintain synchronous methodology at the top level (compatible with IC design tools) while implementing asynchronous-like power efficiency at the individual stage level, thus resolving the conflict between design tool compatibility and power efficiency.
Solution Approach 2:
The patent introduces clock enable signals as an intermediary between the synchronous clock source and the pipeline stage flip-flops. This intermediary layer allows the synchronous design methodology to be maintained at the system level while enabling dynamic power control at the stage level, effectively bridging the gap between synchronous design tool requirements and asynchronous power efficiency goals.
Data Source
AI summary
The embodiments employ a transaction based design methodology to supply clocking when clock pulses are requested. The transactional module receives a clock when it requests a clock pulse and one stage of a logic pipeline is clocked at a time. This methodology reduces dynamic power dissipation by the transactional module from the dynamic power dissipated by traditional synchronous logic designs.