Transaction-Level Equivalence Checking for Handshake Protocol Circuits
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Solution Overview
Problem
Traditional sequential equivalency checking methods fail to determine functional equivalence between circuit designs governed by handshake protocols, as they require cycle-by-cycle matching, which is not feasible, and cannot verify worst-case performance delays.
Innovation Solution
The approach checks circuit designs for equivalence at the transaction level, abstracting timing delays and verifying data transportation and transformation between designs, allowing equivalence checking without cycle-by-cycle output analysis, and supporting different protocols between inputs and outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional sequential equivalency checking is performed with cycle-by-cycle matching, then functional equivalence can be verified for simple designs, but it fails to determine equivalence for designs governed by handshake protocols and cannot verify worst-case performance delays
Solution Approach 1:
The patent applies dynamics by making the equivalence checking method adaptable to different protocol types. The system dynamically adjusts its verification approach based on whether handshake protocols or simple protocols are detected, allowing it to handle both cases effectively rather than being fixed to a single cycle-by-cycle matching approach
Solution Approach 2:
The patent changes the verification parameters from strict cycle-by-cycle timing matching to transaction-level data matching. By altering the comparison criteria to focus on data equivalence rather than temporal alignment, the system can verify handshake protocols where timing relationships are not fixed but data integrity is paramount
2Adaptability or versatility
If transaction-level equivalence checking is performed by abstracting timing delays, then equivalence can be verified for handshake protocols, but detailed timing analysis and worst-case performance verification are not possible
Solution Approach 1:
The patent segments the verification process into two distinct parts: transaction-level equivalence checking and timing analysis. The equivalence checker operates at the transaction level to verify data integrity for handshake protocols, while a separate timing analysis component handles worst-case delay verification, allowing both functions to coexist without interference
3Reliability
If cycle-by-cycle output matching is required, then functional equivalence can be determined for synchronous designs, but verification fails for asynchronous designs with handshake protocols
Solution Approach 1:
The patent creates a universal equivalence checking system that can handle multiple design types through a single integrated approach. The system automatically detects whether a design uses handshake protocols or simple synchronous interfaces and applies the appropriate verification method, making it universally applicable to both asynchronous and synchronous designs without requiring separate verification tools
Data Source
AI summary
An improved approach is provided to implement equivalency checking. A check is performed as to whether two designs are equivalent without needing to analyze their outputs on a cycle-by-cycle basis. Instead, the two designs are checked to see if they are equivalent on the transaction-level. This approach abstracts the timing delays between the two designs, which allows verification of data transportation and transformation between the designs.