Transaction Exception Counting Circuit for Security Detection

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Solution Overview

Problem

Existing data processing systems that handle transactions atomically often suppress synchronous exceptions, preventing the operating system from being aware of transaction failures, which can mask nefarious activities like malicious memory access patterns.

Innovation Solution

Incorporating exception handling circuitry that counts synchronous exceptions during transactions and generates a transaction failure signal when a threshold is reached, allowing the operating system to be notified of repeated exceptions, which can indicate security breaches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If synchronous exceptions are suppressed during transactions, then transaction atomicity is maintained and system stability is improved, but the operating system cannot detect security threats and loss of information occurs

Engineering Contradiction:
Improvetransaction atomicityVSAvoidexception information
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

An exception counting mechanism is introduced as an intermediary between the exception handling circuitry and the operating system. The counter accumulates exception information during transactions and only notifies the OS when a threshold is reached, thus preserving transaction atomicity while preventing information loss about security threats

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

A feedback loop is established where the exception counter monitors exception occurrences and provides feedback to the operating system only when the count reaches a predetermined threshold. This selective feedback mechanism maintains system stability while ensuring critical security information is communicated

Inventive Principle:
Principle #23Feedback

2Reliability

If all synchronous exceptions are notified to the operating system, then security detection capability is improved, but system performance deteriorates due to frequent exception handling

Engineering Contradiction:
Improvesecurity detectionVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

Instead of notifying the operating system about every single exception, the system applies partial action by only notifying when the exception count reaches a threshold. This reduces the frequency of OS interventions while still detecting security threats, thereby maintaining system performance

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The exception notification is transformed from a continuous process to a periodic action triggered only when the threshold is reached. This periodic notification mechanism reduces the overhead on system performance while ensuring security threats are detected

Inventive Principle:
Principle #19Periodic action

3Reliability

If exception counting and threshold notification is implemented, then security threat detection is improved without excessive notifications, but device complexity increases

Engineering Contradiction:
Improvesecurity detection capabilityVSAvoidexception handling circuitry
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system changes the parameter of exception notification from binary (notify/don't notify) to threshold-based (notify when count >= threshold). This parameter change enables security detection without excessive notifications while keeping the additional complexity manageable through a simple counter mechanism

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11481290B2Exception handling in transactions
Publication Date: 2022.10.25 ARM LTD
  • US11481290B2 patent drawing
  • US11481290B2 patent drawing
  • US11481290B2 patent drawing

AI summary

An apparatus and a method of operating a data processing apparatus, and simulators thereof, are disclosed. Data processing circuitry performs data processing operations in response to instructions, where some sets of instructions may be defined as a transaction which are to be performed atomically with respect to other operations performed by the data processing circuitry. When a synchronous exception occurs during a transaction the transaction is aborted and an exception counter is incremented. When the counter reaches a threshold value a transaction failure signal is generated, allowing, if appropriate a response to this number of exceptions causing transaction aborts to be carried out.