On-Chip Transaction Filter Circuit for Debugging Complex ASICs

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Solution Overview

Problem

Debugging complex integrated systems, such as ASICs, is challenging due to latent software or hardware defects that are difficult to isolate and diagnose, especially in systems running multiple parallel operations at high speeds, where recreating error conditions is time-consuming and complex.

Innovation Solution

Implementing transaction filter circuits within the ASIC to monitor core circuits in real-time, log transactions, and take actions such as freezing the communications fabric or interrupting the CPU when specific events occur, allowing for quicker identification and diagnosis of defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Difficulty of detecting and measuring

If transaction filter circuits are implemented to monitor and log all transactions, then debugging capability and defect diagnosis speed are improved, but device complexity and area consumption increase

Engineering Contradiction:
Improvedefect diagnosis capabilityVSAvoidfilter circuit complexity
Core Design Contradiction:
Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The transaction filter circuit is divided into multiple independent filter units, each capable of monitoring specific transaction types or address ranges. This segmentation allows the system to achieve comprehensive monitoring capability while keeping individual filter units simple and manageable, resolving the contradiction between debugging capability and device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The filter circuit is designed with multi-functional capabilities including transaction logging, pattern matching, address range filtering, and multiple action execution (freeze, interrupt, discard). This universal design consolidates multiple debugging functions into a single integrated circuit, improving defect diagnosis capability without proportionally increasing overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If filter circuits log all matching transactions to a buffer, then measurement precision and debugging information quality are improved, but loss of time for data processing and buffer management increases

Engineering Contradiction:
Improvetransaction monitoring precisionVSAvoiddata processing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The filter circuit performs preliminary filtering and pattern matching on transactions before they reach the buffer. By pre-processing transactions and only logging those that match configured patterns, the system achieves high measurement precision while minimizing the time required for buffer management and data processing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The filter circuit extracts only the relevant transaction information that matches the debugging criteria and logs only those specific transactions to the buffer. This selective extraction approach maintains high monitoring precision for relevant events while significantly reducing the overall data processing time by excluding irrelevant transactions from the logging process.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If the system freezes the communications fabric or interrupts CPU upon detecting errors, then reliability and defect isolation capability are improved, but productivity and system availability decrease

Engineering Contradiction:
Improvedefect isolation reliabilityVSAvoidsystem availability
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The filter circuit dynamically adjusts its response behavior based on the severity and type of detected transactions. For critical errors, it freezes the communications fabric or interrupts the CPU to ensure reliable defect isolation. For less severe conditions, it allows continued operation with logging only. This dynamic response strategy maintains high reliability for critical defects while preserving system productivity and availability for non-critical operations.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20220121605A1Methods and systems for address based transaction filters for on-chip communications fabrics
Publication Date: 2022.04.21 PENSANDO SYSTEMS INC
  • US20220121605A1 patent drawing
  • US20220121605A1 patent drawing
  • US20220121605A1 patent drawing

AI summary

A configurable transaction filtering and logging circuit for on-chip communications within a semiconductor chip can store filter patterns. The filter patterns can include an address range filter pattern. The circuit can monitor transactions carried by an on-chip connection fabric. The transactions can be configured to transfer data between a first core circuit and a second core circuit that are also implemented on the semiconductor chip. The circuit can execute one of a set of actions in response to detecting a transaction that matches one of the filter patterns. One of the actions can be logging the transaction to a transaction log buffer in response to detecting that the transaction matches one of the filter patterns.