Transaction ID Allocation via Valid Bits in Network on Chip
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Solution Overview
Problem
Existing network on a chip (NoC) systems face inefficient system bandwidth utilization due to limited transaction IDs, leading to inferior system performance as requests with the same ID are completed in order, resulting in idle cycles and suboptimal processing.
Innovation Solution
Each processing module is assigned an address space, with a subset of the address space designated as Valid Bits, which are associated with unique transaction IDs, allowing for differentiated processing and prioritization of transactions across modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If limited transaction IDs are used in AXI system, then device complexity is reduced, but system bandwidth utilization deteriorates
Solution Approach 1:
The address space is segmented into multiple portions, with each portion assigned to a different processing module. Within each portion, valid bits are selected to generate unique transaction IDs. This segmentation allows multiple processing modules to have dedicated address spaces while maintaining unique transaction IDs, thereby increasing system bandwidth utilization without proportionally increasing overall system complexity
Solution Approach 2:
Each processing module is assigned a specific portion of the address space with locally selected valid bits. This local quality approach ensures that each module has customized transaction ID allocation based on its specific address space requirements, enabling efficient bandwidth utilization for each module while maintaining system-wide coordination
2Device complexity
If same transaction ID is used for multiple requests, then device complexity is reduced, but system performance deteriorates due to idle cycles
Solution Approach 1:
The transaction ID allocation is made dynamic by selecting valid bits from different portions of address spaces for different processing modules. This dynamic allocation ensures that each module can have unique transaction IDs when needed, eliminating idle cycles caused by sequential processing of same-ID requests, while maintaining manageable complexity through systematic bit selection
3Productivity
If out-of-order transaction completion is enabled, then system performance is improved, but device complexity increases
Solution Approach 1:
The invention changes the parameter of transaction ID generation by selecting valid bits from different address space portions for different processing modules. This parameter change enables out-of-order transaction completion by ensuring unique transaction IDs for concurrent requests, thereby improving system performance while managing complexity through systematic parameter assignment rather than complex processing logic
Data Source
AI summary
A system and method for allocating transaction ID in a system with a plurality of processing modules is disclosed. In one embodiment, a method for assigning transaction ID to a processing module in a network on a chip system (NOCS) with a plurality of processing modules is disclosed. An address space is provided to each of the processing modules. A portion of the address space is selected. A subset of the selected portion of the address space for each of the processing module is selected as Valid Bits. The Valid Bits of the processing module is associated to a transaction ID.