Transaction Identifier Expansion Circuitry for Deadlock-Free Interconnects
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Solution Overview
Problem
Existing data processing systems face performance issues due to the risk of cyclic dependency deadlocks in interconnect circuitry, particularly when multiple transactions with the same transaction identifier are issued to different slave devices, which can lead to significant performance impacts and require complex deadlock avoidance schemes that restrict flexibility and increase engineering resources.
Innovation Solution
The introduction of transaction identifier expansion circuitry that compares transaction attributes with predetermined attributes of the target slave device to map initial transaction identifiers to revised identifiers, allowing transactions to proceed without deadlocks, thus avoiding the need for complex deadlock avoidance schemes and maintaining performance by ensuring different transaction identifiers are used for different slave devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple transactions with the same transaction identifier are issued to different slave devices to improve performance through reordering, then system throughput is improved, but the risk of cyclic dependency deadlock increases
Solution Approach 1:
The patent segments the transaction identifier space by creating a mapping between an initial transaction identifier and a revised transaction identifier. This segmentation allows transactions with the same initial identifier to be differentiated by their target slave device through the mapping circuitry, enabling safe reordering while preventing deadlocks.
Solution Approach 2:
The patent introduces a mapping circuitry as an intermediary between the transaction issuance point and the slave devices. This intermediary contains a mapping from an initial transaction identifier to a revised transaction identifier, which prevents deadlocks by ensuring that transactions with the same initial identifier but different target slave devices receive different revised identifiers.
2Reliability
If complex deadlock avoidance schemes are implemented to prevent deadlocks, then system reliability is improved, but device complexity and engineering resources increase
Solution Approach 1:
The patent implements a self-service mechanism where the mapping circuitry automatically manages transaction identifier allocation. The circuitry maintains a mapping from initial to revised transaction identifiers and automatically selects appropriate identifiers, eliminating the need for complex external deadlock avoidance schemes.
Solution Approach 2:
The patent changes the transaction identifier parameter dynamically based on the target slave device. By modifying the transaction identifier from its initial value to a revised value through the mapping circuitry, the system prevents deadlocks without requiring complex avoidance logic.
3Productivity
If transaction reordering is allowed to improve performance, then productivity is improved, but the difficulty of detecting and measuring deadlock conditions increases
Solution Approach 1:
The patent takes preliminary action by pre-establishing the mapping from initial to revised transaction identifiers before transactions are issued. This preliminary mapping ensures that deadlock conditions are prevented in advance, making detection unnecessary while allowing free reordering for performance improvement.
Data Source
AI summary
Transaction identifier expansion circuitry is provided, along with a method of operating such circuitry. The transaction identifier expansion circuitry interfaces between a master device and interconnect circuitry used to couple the master device with a plurality of slave devices to enable transactions to be performed. Transaction analysis circuitry is responsive to each transaction in a sequence of transactions initiated by the master device, to compare at least one attribute of the transaction with predetermined attributes indicative of the target slave device for that transaction. Based on the comparison, an initial transaction identifier is then mapped to one of a plurality of revised transaction identifiers, such that the revised transaction identifier is dependent on the target slave device. Reordering circuitry is then arranged to buffer response transfers received from the interconnect circuitry destined for the master device, with each response transfer having the revised transaction identifier associated therewith. The reordering circuitry then re-orders the response transfers having regard to the original transaction order of those transactions within the sequence of transactions that had the same initial transaction identifier, prior to provision of each response transfer to the master device. By such an approach, the performance of a high performance master device can be maintained, by ensuring that for at least the transactions targeted to a particular subset of the slave devices, no intervention by deadlock avoidance circuitry within the interconnect is required when routing transactions to those slave devices, due to the use of different transaction identifiers when accessing those slave devices.