Transaction Issue Control Circuit for Bus Bandwidth Allocation
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Solution Overview
Problem
Existing bus systems face challenges in efficiently allocating bandwidth among multiple master devices, particularly when one device generates transaction requests at a higher rate than others, as traditional allocation mechanisms like round robin and weighted round robin schemes fail to accurately reflect and meet the varying bandwidth demands of devices in hierarchical bus systems.
Innovation Solution
A control mechanism that regulates the issuing of transaction requests to the bus system by using a target outstanding transaction value with both integer and fractional portions, allowing for a time-averaged number of outstanding requests to correspond to a specific value (N.x), enabling non-integer ratios of bandwidth allocation that better match the demands of different master devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If weighted round robin scheme is used to allocate more time slots to one master device, then that master device can access the bus system more frequently, but the distribution of bus/slave bandwidth among master devices is not accurate and the scheme is difficult to manage in hierarchical bus systems
Solution Approach 1:
The patent changes the control parameter from time slot allocation (weighted round robin) to outstanding transaction request regulation. By controlling the number of outstanding transaction requests allowed from each master device, the system achieves accurate bandwidth allocation proportional to device demand without the complexity of weighted scheduling mechanisms.
Solution Approach 2:
The patent implements a feedback mechanism where the bus system monitors the number of outstanding transaction requests from each master device and dynamically adjusts the rate at which new requests are accepted. This feedback loop ensures that bandwidth allocation automatically adapts to actual device needs and bus utilization conditions.
2Productivity
If round robin mechanism is used to allocate fixed slots to each master device, then each master device has an equal chance of accessing the bus system, but master devices generating requests at higher rates cannot access the bus system more frequently
Solution Approach 1:
The patent transitions from static time slot allocation (round robin) to dynamic request rate control. The bus system dynamically adjusts how many outstanding transaction requests it allows from each master device based on actual bandwidth demands, enabling flexible allocation that adapts to changing conditions without manual reconfiguration.
Solution Approach 2:
The patent changes the allocation parameter from fixed time slots to variable outstanding request counts. This allows the system to allocate bandwidth in proportion to each master device's request generation rate, improving both flexibility and operational efficiency.
3Productivity
If the number of outstanding transaction requests is increased to accommodate higher bandwidth demands, then master devices can access the bus system more frequently, but the bus system becomes more congested and bandwidth distribution becomes less efficient
Solution Approach 1:
The patent uses feedback control where the bus system monitors outstanding transaction request counts and adjusts request acceptance rates accordingly. When congestion is detected, the system automatically reduces the rate at which new requests are accepted from master devices, preventing further congestion while maintaining optimal throughput.
Solution Approach 2:
The patent applies preliminary anti-action by controlling the rate at which transaction requests are issued to the bus system before congestion occurs. By regulating outstanding request counts in advance, the system prevents bus overload and maintains efficient bandwidth distribution.
Data Source
AI summary
Transaction requests requesting a service from the slave device are received from a master device at a transaction interface. The transaction requests are selectively issued to the bus system under control of an issue control circuit. A target outstanding transaction value N.x is received at a control interface. The target outstanding transaction value has an integer portion N and a fractional portion x. The issue control circuit controls the transaction interface to issue the transaction requests to the bus system in dependence upon the target outstanding transaction value so that a time averaged number of outstanding transaction requests corresponds to the target outstanding transaction value.