Transaction Logger for Bus Error Detection
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Solution Overview
Problem
Existing computing devices face challenges in detecting and recording errors, particularly system hangs, due to the lack of mechanisms to preserve transaction data when the device resets, which hinders early error detection and debugging, especially in devices with complex hardware and software interactions.
Innovation Solution
A computing device architecture that includes a transaction logger device to intercept and save records of outstanding transactions initiated by master units, allowing these records to be preserved even when the device restarts, enabling effective error detection and debugging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a cache is used to store transaction information, then error detection capability is improved, but information is lost when the device resets
Solution Approach 1:
The patent applies preliminary action by detecting and responding to reset conditions before they complete. The system monitors for reset signals and proactively saves transaction information to non-volatile storage before the reset actually occurs, ensuring data preservation without interfering with normal device operation.
Solution Approach 2:
The patent introduces an intermediary mechanism - a save logic circuit - that acts as a mediator between the volatile cache and non-volatile storage. This intermediary captures transaction information from the cache and transfers it to persistent storage, bridging the gap between fast but volatile memory and slow but persistent memory.
2Reliability
If transaction logging is implemented continuously, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The patent applies partial action by implementing selective logging - not all transactions are logged continuously, but only those that are outstanding (in-progress) when a reset condition is detected. This reduces the logging overhead while maintaining sufficient information for error analysis.
Solution Approach 2:
The patent applies local quality by implementing logging functionality only where needed - specifically in the transaction logging circuit that monitors the bus interface. Rather than implementing comprehensive system-wide logging, the solution focuses logging resources on capturing critical transaction state information locally at the bus interface level.
3Device complexity
If existing cache is reused for transaction logging, then device complexity is reduced, but logging capability is limited to specific master devices
Solution Approach 1:
The patent applies universality by designing a save logic circuit that can handle transactions from any master device uniformly. The logging mechanism is not tied to specific master devices but rather monitors the bus interface itself, making it universally applicable to all master-slave transactions on the bus regardless of which master initiates them.
Data Source
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AI summary
A computing device includes at least one master unit; at least one slave unit; an interconnect structure configured to route transactions from the at least one master unit to the at least one slave unit; and a transaction logger device configured to intercept and save a record of outstanding transactions sent by the at least one master unit to the interconnect structure. The transaction logger device is further configured to preserve the record of outstanding transactions when at least a part of the computing device is restarted.