Transaction Metadata Bus for Low-Latency Hierarchical ECC
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Solution Overview
Problem
Storage and retrieval of data from memory systems have been a performance bottleneck, with existing error correction codes (ECCs) often resulting in high latency, which limits the computational capabilities of computer systems. Emerging memory technologies require low-latency ECC decoders to maintain reliability and performance.
Innovation Solution
A hierarchical ECC decoder architecture is implemented, using a fast decoder (FD) embedded in the memory device and an accurate decoder (AD) in the storage controller, with transaction metadata providing parity data and validity flags to facilitate low-latency error correction. This architecture allows for efficient error correction and management of memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC decoders are used in memory systems, then error correction capability is maintained, but latency increases and performance decreases
Solution Approach 1:
The ECC decoder is segmented into two hierarchical levels: a fast decoder (FD) implemented in the memory device that handles common error cases quickly, and an accurate decoder (AD) implemented in the storage controller that handles complex error cases. This segmentation allows the system to achieve low latency for most operations while maintaining high correction capability when needed.
Solution Approach 2:
The fast decoder performs preliminary error correction in the memory device before data transfer to the storage controller. By correcting errors that can be detected and fixed with simple parity checks at the source, the system avoids the need for more complex and time-consuming decoding operations later, thereby reducing overall latency.
2Loss of time
If fast decoding is implemented in memory device, then latency is reduced, but correction capability may be insufficient for complex errors
Solution Approach 1:
Transaction metadata acts as an intermediary that carries parity data and validity flags from the memory device to the storage controller. This metadata enables the accurate decoder to determine whether complex decoding is necessary, allowing the fast decoder to handle simple cases quickly while ensuring that complex errors can be corrected by the AD when needed.
Solution Approach 2:
The system uses feedback through transaction metadata (including validity flags and parity data) to inform the storage controller about the state of corrected data. This feedback mechanism allows the accurate decoder to intervene only when the fast decoder indicates that errors may not have been fully corrected, thus maintaining high correction capability without sacrificing latency performance.
Data Source
AI summary
Apparatuses and methods related to providing transaction metadata. Providing transaction metadata includes providing an address of data stored in the memory device using an address bus coupled to the memory device and the controller. Providing transaction metadata also includes transferring the data, associated with the address, from the memory device using a data bus coupled to the memory device and the controller. Providing transaction metadata further includes transferring a sideband signal synchronously with the data bus and in conjunction with the address bus using a transaction metadata bus coupled to the memory device and the controller.