Transaction Ordering Policy for Digital Systems
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Solution Overview
Problem
Current transaction ordering policies in digital systems, such as FIFO and unordered transactions, can lead to performance penalties due to blocking and require requestors to impose order, which complicates system operation and can result in errors, especially in multimedia systems with varying data streams.
Innovation Solution
A transaction ordering policy that allows access requests to specify whether they should be performed in a sequential order, with the controller determining the performance order based on specified constraints, reducing unnecessary blocking and simplifying the ordering process for requestors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FIFO transaction ordering policy is used, then transaction order is maintained, but performance penalty increases due to blocking
Solution Approach 1:
The patent segments transactions into different types (ordered and unordered) based on their specific requirements. Ordered transactions maintain strict sequencing while unordered transactions can proceed independently, allowing the system to optimize performance for each transaction type without compromising overall reliability requirements.
Solution Approach 2:
The transaction ordering policy is made dynamic by allowing different ordering constraints to be applied to different transactions based on their characteristics. The system can switch between strict FIFO ordering for ordered transactions and flexible ordering for unordered transactions, optimizing performance adaptively rather than using a fixed policy.
2Productivity
If unordered transaction policy is used, then performance improves by reducing blocking, but requestors must impose order which complicates system operation
Solution Approach 1:
The system provides self-service by automatically determining and enforcing transaction ordering based on the transaction type indicators. Requestors simply need to mark transactions as ordered or unordered, and the system handles the complexity of maintaining proper sequences automatically, eliminating the need for requestors to actively manage ordering logic.
Solution Approach 2:
The patent changes the parameter of transaction ordering from a fixed system-wide constraint to a flexible, transaction-specific parameter. By allowing each transaction to be marked with its ordering requirements, the system adapts the ordering behavior to match actual performance needs while simplifying requestor operations.
3Reliability
If strict FIFO ordering is enforced, then transaction correctness is ensured, but bus cycles increase due to sequential processing requirements
Solution Approach 1:
The patent segments transactions into ordered and unordered categories, allowing strict FIFO enforcement only where necessary (for ordered transactions) while permitting parallel processing for unordered transactions. This segmentation reduces unnecessary sequential processing delays and minimizes bus cycle usage while maintaining correctness where required.
Solution Approach 2:
Instead of applying full FIFO ordering to all transactions (excessive action), the system applies ordering only to the extent needed (partial action) - specifically to transactions marked as ordered. This partial application of ordering constraints reduces unnecessary waiting time and bus cycle overhead while maintaining correctness for transactions that require it.
Data Source
AI summary
A digital system with an improved transaction ordering policy is disclosed. Individual occurrences of requests for access to common system resources specify whether or not the request is ordered. In some embodiments, the invention includes a memory that holds data, a controller, and at least two processors that generate requests to access the memory data. Each access request includes an indication of whether or not this request is to be performed in a sequential order among other access requests and, if so, an indication of the order. The controller receives the access requests from each processor, determines a performance order for the requests, and provides the access requests to the memory in the performance order. The performance order conforms to the specified order when the access requests so indicate.