Transaction Ordering Circuitry for Interconnect Latency Reduction
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Solution Overview
Problem
Existing interconnect systems face delays due to ordering requirements in transaction processing, particularly when slow peripheral devices hold up faster devices like interrupt controllers, and current solutions either incur high hardware costs or inefficiencies in bus logic.
Innovation Solution
A data processing apparatus that divides recipient devices into subsets based on independence, using a destination device detector and ordering circuitry to maintain order within subsets while allowing independent subsets to process transactions independently, thereby reducing latency and hardware requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single bus is shared by multiple peripheral devices with ordering requirements, then interconnect hardware cost is reduced, but system latency increases due to slow devices holding up fast devices
Solution Approach 1:
The patent segments the set of peripheral devices into multiple subsets based on their ordering requirements and access patterns. Each subset is assigned to a dedicated output port, allowing parallel processing of transactions. This segmentation enables fast devices in one subset to proceed without being blocked by slow devices in other subsets, thereby reducing system latency while maintaining necessary ordering within each subset.
2Loss of time
If separate buses are used for each peripheral device, then system latency is reduced by allowing independent processing, but interconnect hardware cost increases
Solution Approach 1:
The patent creates output ports that serve multiple functions: they can handle transactions for multiple devices within a subset, manage ordering requirements, and operate in parallel with other ports. This multi-functionality allows the system to achieve low latency comparable to separate buses while using fewer physical bus structures, thereby reducing interconnect hardware cost.
3Reliability
If bus logic enforces ordering requirements on all device transactions, then data coherency is maintained, but fast devices are held up by slow devices
Solution Approach 1:
The patent applies ordering requirements locally within each subset of devices rather than globally across all devices. The ordering circuitry enforces ordering only for transactions within the same subset, allowing fast devices in one subset to execute without being blocked by slow devices in other subsets. This local application of ordering maintains data coherency where needed while improving overall device execution speed.
Data Source
AI summary
A data processing apparatus is disclosed that is configured to communicate via an output port with a plurality of devices and to issue a stream of transaction requests to the output port, the stream of transaction requests comprising at least some device transaction requests destined for the plurality of devices. Device transactions are transactions that may affect each other and therefore should be completed in an order in which they are received at the output port in. The output port is configured to output the received transaction requests as a single serial stream of transaction requests. The data processing apparatus comprises: a destination device detector for monitoring the device transaction requests and for determining which of the plurality of devices each of the device transaction requests are destined for; the output port comprises ordering circuitry configured to treat the plurality of devices as at least two subsets of devices, at least one of the subsets comprising at least two devices; the ordering circuitry being configured to receive the stream of transaction requests and to classify each of the device transaction requests into one of the at least two subsets in response to determination of a destination device by said destination device detector, and to maintain said order that said device transaction requests within each subset are received in, such that device transaction requests within each subset are output by the output port and executed by their respective destination devices in the received order, while device transaction requests within different subsets may be output in an order that is different to the received order.