Transaction Router Layout for Cacheable and Non-Cacheable Memory Paths

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Solution Overview

Problem

Integrated circuits experience performance bottlenecks due to cache inefficiencies, particularly when handling cacheable and non-cacheable memory transactions, leading to resource wastage and reduced performance.

Innovation Solution

Implementing transaction routers in the integrated circuit design to early decode memory transactions, routing cacheable transactions directly to cache and non-cacheable transactions bypassing the cache, and optimizing the circuitry based on metadata indicating transaction types.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If all memory transactions are routed through the cache, then cacheable memory transactions can be handled efficiently, but non-cacheable memory transactions cause performance bottlenecks and resource wastage

Engineering Contradiction:

Improvememory transaction handling efficiencyVSAvoidcache resource wastage

Core Design Contradiction:

ProductivityVSLoss of energy

Solution Approach 1:

The patent segments memory transactions into two distinct paths: cacheable transactions are routed through the cache for efficient handling, while non-cacheable transactions are routed directly to memory, bypassing the cache. This segmentation resolves the contradiction by allowing the cache to serve only transactions that benefit from its buffering capabilities, eliminating resource wastage on non-cacheable transactions while maintaining high efficiency for cacheable ones.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a transaction router as an intermediary component that sits between the transaction source and the cache/memory subsystem. This router examines each memory transaction and directs it to the appropriate destination (cache or memory) based on transaction characteristics. The intermediary router enables efficient handling of cacheable transactions while preventing non-cacheable transactions from consuming cache resources, thus resolving the performance bottleneck and resource wastage issues.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If cache resources are increased to handle all transactions, then more memory transactions can be processed, but the integrated circuit size and resource usage increase

Engineering Contradiction:

Improvememory transaction throughputVSAvoidcache resource quantity

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

By segmenting the memory transaction flow into cacheable and non-cacheable paths, the patent ensures that cache resources are allocated only to transactions that require buffering. This segmentation allows the system to maintain high throughput for cacheable transactions using a smaller, more efficient cache, while non-cacheable transactions are handled directly by memory without consuming cache resources.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by providing different handling paths for different types of memory transactions. Cacheable transactions receive the benefit of cache buffering with associated resource allocation, while non-cacheable transactions receive direct memory access without cache involvement. This localized optimization allows the cache to be sized appropriately for its actual workload, reducing overall resource quantity while maintaining productivity.

Inventive Principle:

Principle #3Local quality

3Device complexity

If a unified routing path is used for all memory transactions, then the routing logic is simplified, but performance bottlenecks occur due to mixing cacheable and non-cacheable transactions

Engineering Contradiction:

Improverouting logic complexityVSAvoidmemory transaction performance

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The transaction router acts as an intermediary that adds intelligent decision-making to the memory transaction path. Rather than using a simple unified path, the router examines transaction characteristics and directs them to appropriate destinations. This intermediary component increases routing logic complexity slightly but dramatically improves performance by preventing bottlenecks caused by mixing cacheable and non-cacheable transactions in a single path.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the routing logic into distinct pathways for cacheable and non-cacheable transactions. The transaction router implements this segmentation by evaluating each transaction and directing it to the appropriate path. This segmentation resolves the performance bottleneck by ensuring that non-cacheable transactions do not block or slow down cacheable transactions, while the routing logic remains manageable through clear separation of paths.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS12591527B2Integrated circuit generation with improved interconnect

Publication Date: 2026.03.31 SIFIVE INC

AI summary

Disclosed are systems and methods that include accessing design parameters to configure an integrated circuit design. The integrated circuit design may include a transaction source or processing node to be included in an integrated circuit. The transaction source or processing node may be configured to transmit memory transactions to memory addresses. A compiler may compile the integrated circuit design with the transaction source or processing node to generate a design output. The design output may be configured to route memory transactions based on their targeting cacheable or non-cacheable memory addresses. The design output may be used to manufacture an integrated circuit.