Transactional Buffered Memory Early Identification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current interconnect architectures in computing systems face challenges in meeting the increasing demand for high-performance communication and power efficiency, particularly in server environments and mobile devices, as they struggle to scale bandwidth and manage complex interconnections effectively.
Innovation Solution
The development of a High Performance Interconnect (HPI) architecture that employs a layered protocol stack, including a transaction layer, link layer, and physical layer, with features such as credit-based flow control, virtual channels, and embedded clocking, to enable efficient data transfer and manage power consumption across multiple processor sockets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional multi-drop buses are used for interconnect, then electrical communication is simplified, but bandwidth and communication performance deteriorate
Solution Approach 1:
The patent segments the interconnect architecture into multiple point-to-point links instead of using a single multi-drop bus. Each processor socket communicates through dedicated serial links, dividing the communication burden and enabling simultaneous data transfers across multiple channels, thereby increasing overall bandwidth while maintaining manageable complexity
Solution Approach 2:
The patent transitions from a single-dimension multi-drop bus architecture to a multi-dimensional mesh-like interconnect fabric with multiple routing paths. This dimensional expansion allows data to travel through alternative routes and enables parallel communication channels, significantly boosting bandwidth capacity
2Productivity
If the number of processor sockets is increased, then computing power is improved, but interconnect communication demand increases
Solution Approach 1:
The patent replaces traditional parallel electrical buses with serial point-to-point interconnects that use differential signaling. This substitution enables higher data rates at lower power consumption per bit, allowing the system to scale to multiple processor sockets without proportionally increasing power demand
Solution Approach 2:
The patent implements periodic clocking and training sequences that allow the interconnect to operate efficiently at various power states. The serial links can be dynamically activated or deactivated based on communication needs, reducing power consumption when full bandwidth is not required while supporting high-performance operation when multiple sockets are actively communicating
3Adaptability or versatility
If existing interconnect architectures are used, then current communication needs are met, but future high-rate demand cannot be satisfied
Solution Approach 1:
The patent implements dynamic link training and equalization that automatically adapts to different signal conditions and distances. The interconnect architecture can dynamically adjust signaling rates and voltage levels, enabling it to scale from current communication needs to future high-rate demands without requiring complete redesign
Solution Approach 2:
The patent employs variable signaling rates and adjustable voltage levels in the serial interconnect protocol. These parameter changes allow the system to optimize performance for different workloads and distance requirements, providing a scalable path from current to future data transfer rate demands while maintaining compatibility with existing designs
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.