Transactional Buffered Memory Error Handling Through TID Tracking
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Solution Overview
Problem
As computing systems evolve with increased complexity and demand for higher performance and power efficiency, existing interconnect architectures struggle to efficiently manage communication between components, particularly in high-performance computing environments like servers and mobile ecosystems, where different market segments require varying aspects of interconnect architectures.
Innovation Solution
A new High Performance Interconnect (HPI) architecture is introduced, featuring a layered protocol stack with transaction, link, and physical layers, supporting point-to-point links, credit-based flow control, and flexible routing, enabling efficient data transfer and management of bandwidth demands across diverse computing platforms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional multi-drop buses are used for interconnect architecture, then electrical communication is simplified, but communication speed and bandwidth are insufficient for high-performance computing
Solution Approach 1:
The patent segments the interconnect architecture into multiple point-to-point links instead of using a single multi-drop bus. Each link operates independently at higher speeds, allowing parallel communication channels that collectively provide greater bandwidth while maintaining simpler individual link designs.
Solution Approach 2:
The patent transitions from a single-dimension multi-drop bus topology to a multi-dimensional mesh-like topology with multiple point-to-point links. This dimensional expansion allows data to travel through multiple parallel paths, increasing effective communication speed and bandwidth without requiring each individual path to be excessively complex.
2Productivity
If multiple physical processors and cores are added to increase computing power, then processing capability is improved, but communication overhead and interconnect demands increase
Solution Approach 1:
The patent implements credit-based flow control that maintains continuous data flow between processors through buffered links. Credits are pre-allocated and replenished, allowing processors to continuously send data without waiting for acknowledgments, thereby reducing communication overhead and energy waste from idle periods while supporting multiple high-performance cores.
Solution Approach 2:
The patent introduces buffered links as intermediary components between processors. These buffers absorb communication variability and decouple processors from direct synchronization requirements, reducing the energy overhead of coordination and allowing multiple cores to operate more independently while maintaining system coherence.
3Productivity
If buffered memory protocol is implemented, then data transfer efficiency is improved, but error detection and handling complexity increases
Solution Approach 1:
The patent implements error detection codes that are automatically generated and checked by the buffered memory protocol itself. The protocol includes built-in mechanisms for detecting and handling errors without requiring external intervention, allowing efficient data transfer while managing error handling complexity through self-contained error management features.
4Productivity
If credit-based flow control is used, then bandwidth utilization is improved, but protocol complexity increases
Solution Approach 1:
The patent implements credit-based flow control where credits are pre-allocated in advance rather than negotiated in real-time. This partial automation of the flow control process allows high bandwidth utilization through buffered links while reducing protocol complexity by eliminating the need for complex dynamic credit negotiation mechanisms during data transfer.
Data Source
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AI summary
An apparatus comprises a buffer chip comprising a memory controller to interface with a memory and convert memory requests into a memory specific protocol corresponding to the memory, a receiver to receive a particular memory request from a processor device over a transactional memory link, a transmitter to send a read return to the processor device, the read return comprising a plurality of packets, wherein the plurality of packets comprises an initial headered packet followed by a headerless packet, the headered packet comprises a header flit and a first number of data flits, the headerless packet comprises a second number of data flits, the second number is less than the first number, the header flit comprises a request transaction identifier (TID) corresponding to data in the first number of data flits, each of the first number of data flits comprises a TID corresponding to data in the second number of data flits, and each of the second number of data flits comprises a TID for data in a subsequent headerless packet.