Transactional Memory Atomic Look-up Add Lock for Network Processors
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Solution Overview
Problem
Network processor integrated circuits face challenges in efficiently managing packet traffic and data structures due to limitations in processing power and memory access, particularly in handling hash operations and logging packet and byte count information.
Innovation Solution
The Island-Based Network Flow Processor (IB-NFP) employs a novel transactional memory with a configurable Command/Push/Pull (CPP) data bus, enabling Atomic Look-up, Add, and Lock (ALAL) commands and Stats Add-and-Update (AU) operations, along with a hardware trie structure for efficient lookup operations, utilizing a state machine array and pipeline architecture to manage hash tables and data structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple microengines access the same memory resources via a common bus, then processing power is increased, but memory access efficiency and throughput are limited by bus contention
Solution Approach 1:
The patent segments the common memory resource into multiple transactional memory sets, with each microengine having dedicated access to specific sets. This segmentation eliminates bus contention by allowing parallel access to different memory sets, thereby maintaining high processing power while improving memory access efficiency and throughput.
2Device complexity
If traditional memory access operations are used, then simplicity is maintained, but atomicity of compound operations cannot be guaranteed
Solution Approach 1:
The patent merges multiple discrete memory operations (lookup, add, lock) into a single atomic transactional memory operation. The transactional memory controller receives a compound operation request and executes all sub-operations atomically, ensuring that either all operations complete successfully or none do. This maintains simplicity for the user while guaranteeing atomicity, resolving the contradiction between operational simplicity and reliability.
3Ease of operation
If hash operations and logging operations are performed separately, then operational clarity is maintained, but processing overhead increases
Solution Approach 1:
The patent combines hash operations and logging operations into a single atomic transactional memory operation. The transactional memory controller processes both operations simultaneously within one transaction, eliminating the overhead of separate memory access operations while maintaining operational clarity through a unified interface. This resolves the contradiction by reducing processing overhead without sacrificing ease of operation.
Data Source
AI summary
A transactional memory (TM) receives an Atomic Look-up, Add and Lock (ALAL) command across a bus from a client. The command includes a first value. The TM pulls a second value. The TM uses the first value to read a set of memory locations, and determines if any of the locations contains the second value. If no location contains the second value, then the TM locks a vacant location, adds the second value to the vacant location, and sends a result to the client. If a location contains the second value and it is not locked, then the TM locks the location and returns a result to the client. If a location contains the second value and it is locked, then the TM returns a result to the client. Each location has an associated data structure. Setting the lock field of a location locks access to its associated data structure.