Transactional Memory CAMR Lookup for Network Processor Throughput
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Solution Overview
Problem
Network processor integrated circuits face challenges in efficiently handling increased throughput requirements due to limitations in processing power and memory access, particularly in identifying data structures using hash functions and logging packet and byte count information.
Innovation Solution
The Island-Based Network Flow Processor (IB-NFP) employs a novel transactional memory with a configurable Command/Push/Pull (CPP) data bus and dedicated hardware circuits, including an atomic engine, memory unit, and data bus interface, to perform Atomic Look-up Add and Lock (ALAL) and Stats Add-and-Update (AU) commands, as well as a hardware trie structure for efficient lookup operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple microengines are employed to increase processing power, then throughput is improved, but memory contention and processing complexity increase
Solution Approach 1:
The system segments processing functions into dedicated hardware circuits (lookup engine, atomic engine, stats engine) separate from microengines. Each engine handles specific operations (CAMR lookups, atomic memory operations, statistics updates) independently, allowing multiple microengines to operate in parallel without contending for the same processing resources, thus increasing throughput while managing complexity through functional separation.
Solution Approach 2:
The patent introduces a transactional memory system with dedicated hardware engines as intermediaries between microengines and memory. The atomic engine provides lock-free atomic operations, the lookup engine handles hash table and trie operations, and the stats engine manages statistics updates. These intermediaries absorb the complexity of memory management and data structure operations, allowing microengines to focus on packet processing while maintaining high throughput.
2Speed
If hash functions and hash tables are used to identify data structures, then packet classification speed is improved, but memory access contention increases
Solution Approach 1:
The system pre-organizes data into hash tables and tries with predetermined structures and bucket allocations. The lookup engine pre-calculates hash values and determines the appropriate data structure (hash table vs. trie) based on the operation type. This preliminary organization allows O(1) or O(log n) lookup time without requiring complex runtime memory allocation or restructuring, maintaining high classification speed while reducing memory access contention through predictable access patterns.
Solution Approach 2:
The patent implements multi-dimensional data structures including hash tables with multiple buckets, tries with multiple levels, and nested data structures. The lookup engine can switch between different data structure dimensions (e.g., from hash table to trie) based on the specific lookup requirements. This dimensional approach allows parallel access paths and reduces contention by distributing memory accesses across multiple dimensions rather than a single linear structure.
3Reliability
If atomic operations are performed on packets and packet data, then data integrity is improved, but processing time increases
Solution Approach 1:
The patent replaces software-based atomic operations with hardware-implemented atomic engines that provide lock-free atomic memory operations. The atomic engine uses specialized hardware circuits to perform atomic read-modify-write operations, compare-and-swap operations, and other atomic primitives directly in hardware. This substitution eliminates the overhead of software locking mechanisms, context switching, and memory barriers, maintaining data integrity through hardware-enforced atomicity while significantly reducing processing time compared to software-based approaches.
Data Source
AI summary
A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a base address, a starting bit position, and a mask size. In response to the command, the TM pulls an input value (IV). A selecting circuit within the TM uses the starting bit position and the mask size to select a first portion of the IV. The first portion of the IV and the base address value are summed to generate a memory address. The memory address is used to read a word containing multiple result values and multiple reference values from memory. A second portion of the IV is compared with each reference value using a comparator circuit. A result value associated with the matching reference value is selected using a multiplexing circuit and a select value generated by the comparator circuit. The TM sends the selected result value to the processor.