Transactional Memory Direct 32-bit Lookup for Network Processing
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Solution Overview
Problem
Network processor integrated circuits face challenges in efficiently handling increased throughput requirements due to limitations in processing power and memory access, particularly in identifying data structures using hash functions and logging packet and byte count information.
Innovation Solution
The Island-Based Network Flow Processor (IB-NFP) employs a novel transactional memory with a configurable Command/Push/Pull (CPP) data bus and dedicated hardware circuits, including an atomic engine and stats engine, to perform atomic operations and update counts efficiently, using commands like Atomic Look-up Add and Lock (ALAL) and Stats Add-and-Update (AU) to manage hash tables and packet counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple microengines access the same memory resources via a common bus, then processing power is increased, but memory contention and access efficiency deteriorate
Solution Approach 1:
The patent segments the common memory resources into multiple dedicated memory banks (first memory bank, second memory bank, third memory bank) that can be accessed simultaneously by different microengines. Each microengine can access different memory banks in parallel, eliminating the bottleneck of a single common bus while maintaining increased processing power through multiple microengines.
2Adaptability or versatility
If hash table operations are performed using software-based memory access, then flexibility is maintained, but processing speed deteriorates
Solution Approach 1:
The patent introduces a dedicated lookup engine as an intermediary hardware component between the microengines and the memory banks. This lookup engine specifically handles hash table operations with optimized hardware circuits for hash function calculation and table traversal, providing both the speed of hardware processing and the flexibility of programmable hash algorithms through configurable hash functions.
Solution Approach 2:
The patent replaces software-based memory access mechanisms with dedicated hardware circuits for hash table operations. The lookup engine uses hardware-implemented hash functions, comparators, and memory access circuits to perform table lookups in parallel, substituting the sequential software execution model with concurrent hardware operations that maintain algorithmic flexibility through configurable parameters.
3Reliability
If packet count and byte count information are logged sequentially, then memory consistency is maintained, but throughput deteriorates
Solution Approach 1:
The patent segments the logging operations into parallel paths by providing separate dedicated memory banks for different types of statistics (packet counts, byte counts, flow statistics). Multiple microengines can simultaneously update different statistics in different memory banks without causing contention, maintaining consistency within each bank while achieving high aggregate throughput through parallel updates.
Solution Approach 2:
The patent combines multiple logging operations into a single unified memory access cycle by allowing simultaneous writes to different memory banks. Instead of sequentially logging packet counts, byte counts, and flow statistics one after another, the system merges these operations into parallel concurrent writes, achieving both consistency (through atomic operations) and high throughput (through parallel execution).
Data Source
AI summary
A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a base address, a starting bit position, and a mask size. In response to the lookup command, the TM pulls an input value (IV). The TM uses the starting bit position and the mask size to select a portion of the IV. A first sub-portion of the portion of the IV and the base address are summed to generate a memory address. The memory address is used to read a word containing multiple result values (RVs) from memory. One RV from the word is selected using a multiplexing circuit and a second sub-portion of the portion of the IV. If the selected RV is a final value, then lookup operation is complete and the TM sends the RV to the processor, otherwise the TM performs another lookup operation based upon the selected RV.