Transactional Memory Lookup Engine for Network Processor Throughput
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Solution Overview
Problem
Network processor integrated circuits face challenges in efficiently performing high-throughput packet processing and lookup operations due to limitations in existing memory architectures, particularly in handling large volumes of packet data and complex hash operations.
Innovation Solution
The Island-Based Network Flow Processor (IB-NFP) employs a novel transactional memory with a lookup engine that includes a state machine selector, arbiter, translator, and pipeline, allowing for efficient TCAM 32-bit and PMM 32-bit lookup operations across a configurable Command/Push/Pull data bus, reducing bus transactions and enhancing processing power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple microengines are employed to increase processing power, then throughput is improved, but device complexity increases
Solution Approach 1:
Multiple microengines are merged into a single integrated circuit with shared memory resources and a common command/push/pull bus. This allows them to operate in parallel for increased throughput while sharing infrastructure to control complexity growth.
Solution Approach 2:
The transactional memory unit is designed to serve multiple microengines simultaneously, providing universal access to memory resources. This multi-functional design allows the same memory structure to support varying numbers of microengines based on throughput requirements.
2Productivity
If hash functions and hash tables are used to find data structures, then packet processing capability is improved, but processing time increases
Solution Approach 1:
Hash tables are pre-computed and stored in memory before packet processing begins. This preliminary action allows O(1) lookup time during actual packet processing, eliminating the need to compute hash functions repeatedly for each packet.
Solution Approach 2:
The patent replaces software-based hash computation and table traversal with hardware-accelerated lookup circuits. This substitution of mechanical/computational processes with dedicated hardware reduces processing time significantly.
3Measurement precision
If packet count and byte count information is logged to memory tables, then accounting accuracy is improved, but memory access overhead increases
Solution Approach 1:
Packet count and byte count logging is merged with the main data structure storage in the same memory unit. This combining eliminates separate memory access operations for accounting, reducing overhead while maintaining accurate counting.
Solution Approach 2:
The transactional memory unit performs accounting updates automatically as part of its normal operation. When packets are processed and stored, the same transactional memory incrementally updates count and byte count fields without requiring separate logging operations.
Data Source
AI summary
A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs), multiple reference values, and multiple mask values from memory. A selecting circuit within the TM uses a starting bit position and a mask size to select a portion of the IV. The portion of the IV is a lookup key value (LKV). The LKV is masked by each mask value thereby generating multiple masked values. Each masked value is compared to a reference value thereby generating multiple comparison values. A lookup table generates a selector value based upon the comparison values. A result value is selected based on the selector value. The selected result value is then communicated to the processor via the bus.