Transactional Memory Lookup Engine for Network Processor Bus Optimization
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Solution Overview
Problem
Network processor integrated circuits face challenges in efficiently performing high-throughput packet processing and lookup operations due to limitations in existing memory architectures, particularly in handling large volumes of packet data and complex hash operations.
Innovation Solution
The Island-Based Network Flow Processor (IB-NFP) employs a novel transactional memory with a configurable Command/Push/Pull (CPP) data bus, featuring a lookup engine with a state machine selector, arbiter, translator, and pipeline, which enables efficient TCAM and PMM 32-bit lookup operations by minimizing bus transactions and utilizing dedicated hardware for state machine operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple microengines access the same memory resources via a common command/push/pull bus, then processing power is increased, but bus contention and transaction overhead increase
Solution Approach 1:
The patent segments the monolithic bus interface into multiple dedicated hardware engines, each with its own state machine and processing pipeline. Each engine can independently initiate and execute bus transactions, eliminating the need for software-managed arbitration and reducing bus contention. This segmentation allows multiple engines to operate in parallel while maintaining simple individual transaction protocols.
Solution Approach 2:
Each hardware engine is equipped with its own state machine that autonomously manages the complete bus transaction lifecycle - from initiating the transaction, to receiving responses, to processing data - without requiring software intervention. The state machines self-manage arbitration, timing, and protocol state transitions, freeing the microengines to focus on computational tasks while the hardware engines handle bus protocol complexity independently.
2Adaptability or versatility
If software manages bus transactions and memory access, then flexibility is maintained, but processing throughput decreases due to software overhead
Solution Approach 1:
The patent introduces dedicated hardware engines as intermediaries between the microengines and the memory/bus system. These engines act as autonomous agents that translate high-level microengine requests into detailed bus transaction sequences, handling protocol states, arbitration, and data formatting. The microengines retain flexibility by issuing simple commands, while the hardware intermediaries manage the complex bus interaction details in hardware, achieving both flexibility and high throughput.
3Adaptability or versatility
If general-purpose processors handle lookup operations, then versatility is maintained, but lookup speed and efficiency decrease
Solution Approach 1:
The patent replaces the mechanical/software-based lookup execution model with dedicated hardware engines that perform lookup operations using hardware state machines and comparison logic. The hardware engines can simultaneously initiate multiple bus transactions to different memory locations and process incoming data streams in parallel, achieving lookup speeds that are orders of magnitude faster than software-based approaches while maintaining the ability to handle various lookup types through configurable hardware parameters.
4Quantity of substance
If bus bandwidth is shared among multiple microengines, then resource utilization is improved, but transaction latency increases
Solution Approach 1:
The patent segments the bus transaction management function into multiple independent hardware engines, each capable of autonomous transaction initiation and execution. This segmentation allows multiple engines to operate in parallel on the same bus, effectively multiplying the bus utilization capacity. Each engine maintains its own transaction state and timing, eliminating the serialization delays that would occur with software-managed arbitration while still sharing the physical bus resources efficiently.
Data Source
AI summary
A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs), multiple reference values, and multiple prefix values from memory. A selecting circuit within the TM uses a starting bit position and a mask size to select a portion of the IV. The portion of the IV is a lookup key value (LKV). Mask values are generated based on the prefix values. The LKV is masked by each mask value thereby generating multiple masked values that are compared to the reference values. Based on the comparison a lookup table generates a selector value that is used to select a result value. The selected result value is then communicated to the processor via the bus.