Transactional Memory Cache Coherence via Pre-Invalidation
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Solution Overview
Problem
Existing transactional memory systems face inefficiencies due to increased collision rates as parallelism levels rise, leading to performance degradation, and the pre-invalidation technique cannot be directly combined with hardware transactional memory without contradicting the requirement of hiding the data state during modification.
Innovation Solution
A predictive mechanism is introduced to conditionally place data in the last level cache instead of private cache lines, allowing pre-invalidation of corresponding private cache lines, thereby reducing rollback caused by data conflicts and enhancing prediction accuracy and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the level of parallelism is increased in transactional memory systems, then the performance and scalability are improved, but the collision rate increases causing excessive rolling back which negatively impacts program performance
Solution Approach 1:
The patent applies pre-invalidation technique by invalidating shared data in the cache of the current processor before the transactional memory operation completes. This preliminary action prevents other processors from reading stale data, reducing the need for rolling back transactions due to conflicts, thus improving system performance while maintaining data integrity
2Reliability
If the pre-invalidation technique is directly applied to existing transactional memory design, then conflicts when modifying shared data are reduced, but it directly contradicts with the transactional memory design requirement that state must be hidden during modification
Solution Approach 1:
The patent makes the cache coherence policy selective rather than universal. Pre-invalidation is applied locally only to the specific cache lines that are being modified by the transactional memory operation, while other cache lines maintain the traditional transactional memory hiding behavior. This resolves the contradiction by applying pre-invalidation only where necessary rather than globally
Solution Approach 2:
The patent segments the cache coherence management into different regions: modified cache lines that require pre-invalidation and non-modified cache lines that maintain traditional transactional memory behavior. This segmentation allows the system to combine pre-invalidation and hardware transactional memory without direct contradiction
3Adaptability or versatility
If multiple threads are allowed to run in parallel with transactional memory, then the parallelism is increased, but the collision rate increases causing excessive rolling back
Solution Approach 1:
The patent uses feedback from the transactional memory system to trigger pre-invalidation. When a transactional memory operation modifies shared data, this feedback triggers the pre-invalidation of the corresponding cache lines in the current processor's cache, creating a proactive mechanism that prevents future conflicts and reduces rolling back
Data Source
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AI summary
A multiprocessor system providing transactional memory. A first processor initiates a transaction which includes reading first data into a private cache of the first processor, and performing a write operation on the first data in the private cache of the first processor. In response to detecting that prior to the write operation the first data was last modified by a second processor, the first processor writes the modified first data into a last level cache (LLC) accessible by the multiple processors. The system sets a cache line state index string to indicate that the first data written into the LLC was last modified by the first processor, invalidates the first data in the private cache of the first processor, and commits the transaction to the transactional memory system. This allows more efficient accesses to the data by the multiple processors.