Transactional Memory Split 32-bit Lookup for Network Processors
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Solution Overview
Problem
Network processor integrated circuits face challenges in efficiently handling increased throughput requirements due to limitations in processing power and memory access, particularly in performing lookup operations across large datasets.
Innovation Solution
The Island-Based Network Flow Processor (IB-NFP) employs a novel transactional memory with a configurable Command/Push/Pull (CPP) data bus, allowing for efficient lookup operations through a state machine-based lookup engine that performs SPLIT 32-bit and ALUT 32-bit lookup commands, reducing bus transactions and enhancing processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional memory access methods are used in network processors, then memory operations can be performed, but processing throughput is limited due to multiple bus transactions required for lookup operations
Solution Approach 1:
The patent combines the comparison logic and memory access functions into a single integrated circuit within the transactional memory. The comparison unit compares the lookup key with stored keys, and the memory unit retrieves corresponding data, all within one bus transaction. This merging eliminates the need for separate comparison and memory access operations, thereby reducing bus transaction time and improving processing throughput.
Solution Approach 2:
The patent pre-stores comparison keys and their associated data in the transactional memory's memory unit. By having the comparison keys already available in the memory unit, the system can perform lookups by simply comparing the input key against pre-stored keys and retrieving the corresponding data in a single operation, eliminating the need for preliminary comparison operations before memory access.
2Productivity
If multiple bus transactions are used for lookup operations, then comprehensive data can be accessed, but processing efficiency decreases due to increased transaction overhead
Solution Approach 1:
The patent merges the comparison unit and memory unit into a single integrated circuit, allowing both comparison and data retrieval to occur within one bus transaction. This integration simplifies the bus transaction process by eliminating multiple separate transactions, thereby improving lookup operation efficiency without significantly increasing device complexity.
Solution Approach 2:
The integrated circuit performs multiple functions including comparison, data retrieval, and result output within a single unit. The comparison unit compares lookup keys, the memory unit stores and retrieves data, and the result unit outputs findings, all within one transactional memory structure. This multi-functionality reduces the need for separate dedicated circuits for each operation, simplifying the overall system while improving efficiency.
Data Source
AI summary
A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address, a starting bit position, and a mask size. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs) and multiple threshold values (TVs) from memory. A selecting circuit within the TM uses the starting bit position and mask size to select a portion of the IV. The portion of the IV is a lookup key value (LKV). The multiple TVs define multiple lookup key ranges. The TM determines which lookup key range includes the LKV. A RV is selected based upon the lookup key range determined to include the LKV. The lookup key range is determined by a lookup key range identifier circuit. The selected RV is selected by a result value selection circuit.