Transactional Memory Stats Add-and-Update for Low-Latency Packet Processing
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Solution Overview
Problem
Network processor integrated circuits face challenges in efficiently handling increased throughput requirements for packet processing and data structure lookups due to limitations in sequential logic elements and memory access mechanisms.
Innovation Solution
The Island-Based Network Flow Processor (IB-NFP) employs a novel transactional memory with a hardware trie structure and command/push/pull data bus architecture, enabling atomic look-up, add, and lock operations, as well as stats add-and-update commands, to optimize data access and processing without sequential logic elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple microengines access the same memory resources via a common bus, then processing power is increased, but memory contention and access latency increase
Solution Approach 1:
The common memory bus is segmented into multiple dedicated memory buses, with each microengine having its own dedicated memory access path. This segmentation eliminates contention on the common bus while maintaining high processing power through parallel memory access operations.
Solution Approach 2:
A memory management unit acts as an intermediary between microengines and memory resources, coordinating access to eliminate contention. The MMU manages memory allocation and access timing to reduce latency while maintaining high throughput for multiple microengines.
2Ease of operation
If sequential logic elements are used in the trie structure, then lookup operations can be performed, but processing speed is limited by sequential dependencies
Solution Approach 1:
The trie lookup operation is divided into periodic clock cycles, with each cycle processing a specific level of the trie structure. This periodic decomposition allows parallel processing of different trie levels while maintaining the logical sequentiality of the lookup operation.
Solution Approach 2:
Trie nodes and their associated data are pre-loaded into on-chip memory before lookup operations begin. This preliminary action eliminates the need for sequential memory access during the actual lookup, enabling high-speed parallel processing while maintaining lookup correctness.
Data Source
AI summary
A transactional memory (TM) of an island-based network flow processor (IB-NFP) integrated circuit receives a Stats Add-and-Update (AU) command across a command mesh of a Command/Push/Pull (CPP) data bus from a processor. A memory unit of the TM stores a plurality of first values in a corresponding set of memory locations. A hardware engine of the TM receives the AU, performs a pull across other meshes of the CPP bus thereby obtaining a set of addresses, uses the pulled addresses to read the first values out of the memory unit, adds the same second value to each of the first values thereby generating a corresponding set of updated first values, and causes the set of updated first values to be written back into the plurality of memory locations. Even though multiple count values are updated, there is only one bus transaction value sent across the CPP bus command mesh.