Transactional Memory Store Buffer Commit Latency
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Solution Overview
Problem
Transactional memory systems face performance degradation due to unnecessary memory system bus bandwidth consumption and delays when committing transactions with no buffered stores, as processors signal and wait for non-existent store-marks in the L2 cache.
Innovation Solution
A processor system that sets a stores_encountered indicator during transactional execution, signaling the cache to commit stores only if stores were buffered, and internally generating a PASS signal if no stores were buffered, thereby avoiding unnecessary resource usage and delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor signals the L2 cache to lock store-marked cache lines and commit stores during transaction completion, then memory atomicity is preserved, but memory system bus bandwidth is consumed and commit latency increases when no stores were buffered
Solution Approach 1:
The patent applies partial action by conditionally executing the store commitment process only when stores were actually buffered during transaction execution. The stores_encountered indicator tracks whether stores occurred, and the commit process is partially executed (skipping the L2 cache signaling step) when no stores were buffered, thereby avoiding unnecessary bus transactions and reducing commit latency while maintaining atomicity when needed.
2Productivity
If the processor signals the L2 cache to commit stores, then store-marks are removed and cache lines are unlocked, but unnecessary bus bandwidth consumption occurs when no stores were buffered
Solution Approach 1:
The system performs partial action by conditionally executing the L2 cache commit sequence based on the stores_encountered indicator. When no stores were buffered, the system skips the TX_DONE signal transmission and associated bus transactions, thereby preserving memory system bus bandwidth while maintaining correct behavior for transactions that did buffer stores.
3Reliability
If the processor waits for PASS signal from L2 cache before resuming execution, then commit completion is confirmed, but execution is delayed when no stores were buffered
Solution Approach 1:
The patent implements partial action by conditionally waiting for the PASS signal based on whether stores were buffered. When stores_encountered is clear (no stores buffered), the processor skips the wait for PASS signal and directly resumes execution, improving speed. When stores were buffered, the system maintains reliable confirmation by waiting for the PASS signal before resuming.
Data Source
AI summary
Embodiments of the present invention provide a system that executes transactions on a processor that supports transactional memory. The system starts by executing the transaction on the processor. During execution of the transactions, the system places stores in a store buffer. In addition, the system sets a stores_encountered indicator when a first store is placed in the store buffer during the transaction. Upon completing the transaction, the system determines if the stores_encountered indicator is set. If so, the system signals a cache to commit the stores placed in the store buffer during the transaction to the cache and then resumes execution of program code following the transaction when the stores have been committed. Otherwise, the system resumes execution of program code following the transaction without signaling the cache.