Transactional Memory Subsystem Hardware Remapping

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Solution Overview

Problem

Existing transaction management systems in computing architectures face complexity and high software overhead due to the need for managing transactions as a set of instructions that must either be fully completed or failed, without partial completion, which complicates memory operations and increases overhead.

Innovation Solution

A memory subsystem operates using a transaction protocol that remaps physical memory, creating temporary copies of remapping tables for atomic transactions, ensuring that either all or none of the write operations are successfully executed, and maintains a master remapping table for consolidating changes upon successful completion or reverting upon failure, thereby reducing software complexity and memory overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If transaction management is implemented using traditional software-based approaches, then transactions can be managed with flexibility, but software complexity and overhead increase significantly

Engineering Contradiction:
Improvetransaction management flexibilityVSAvoidsoftware overhead
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent replaces the software-based transaction management system with a hardware-based memory subsystem that natively supports transactions. The memory controller implements transaction protocols and atomic operations directly in hardware, eliminating the need for complex software overhead while maintaining transactional flexibility through dedicated circuitry and control logic.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If temporary copies of memory contents are created for each transaction, then data integrity is ensured through atomic operations, but memory overhead increases

Engineering Contradiction:
Improvedata integrityVSAvoidmemory overhead
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent segments the memory subsystem into distinct functional components including a transaction engine, buffer memory for temporary copies, and main memory. This segmentation allows temporary copies to be created only in the buffer portion when needed for transactions, rather than duplicating entire memory contents, thereby reducing overall memory overhead while maintaining data integrity through controlled copying.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by creating temporary copies only for the specific data blocks being modified during a transaction, rather than copying entire memory regions. The buffer memory allocates space dynamically based on the actual transaction scope, ensuring that memory overhead is proportional to the transaction size rather than a fixed large allocation.

Inventive Principle:
Principle #3Local quality

3Productivity

If multiple transactions are executed concurrently, then system productivity improves, but managing atomic operations and conflicts becomes more complex

Engineering Contradiction:
Improvetransaction execution speedVSAvoidtransaction management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a transaction engine as an intermediary component between the processor and memory subsystem. This dedicated hardware unit manages concurrent transactions by coordinating access to the buffer memory, handling commit/abort protocols, and resolving conflicts through hardware-based mechanisms, thereby simplifying concurrent transaction management compared to software-based approaches.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10083122B2Transactional memory
Publication Date: 2018.09.25 MICRON TECHNOLOGY INC
  • US10083122B2 patent drawing
  • US10083122B2 patent drawing
  • US10083122B2 patent drawing

AI summary

Subject matter disclosed herein relates to techniques to perform transactions using a memory device.