Transactor-Based Framework for Asynchronous IC Emulation Links
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Solution Overview
Problem
Existing emulation systems face performance bottlenecks due to the limitations of Select I/O in transmitting cycle-accurate data between integrated circuits, especially as circuit design size increases, leading to reduced emulation clock frequencies and inefficient partitioning and implementation processes.
Innovation Solution
A transactor-based framework is introduced, where each integrated circuit includes an originator circuit, a completer transactor circuit, and transceiver circuits to synchronize and convey request and response data over asynchronous communication links, allowing for optimized clock rates and parallel processing of circuit design partitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Select I/O is used to transmit cycle accurate data between ICs, then data transmission reliability is maintained, but emulation clock frequency decreases due to multiplexing ratios
Solution Approach 1:
The patent introduces transactor circuits as intermediary components between the synchronous emulation domain and asynchronous communication links. These transactors translate and buffer data, allowing Select I/O to maintain its reliable cycle-accurate operation while the asynchronous interface handles high-speed data transmission independently, thus resolving the conflict between reliability and speed
Solution Approach 2:
The patent segments the data transmission path into distinct synchronous and asynchronous domains. The emulation clock domain maintains cycle-accurate timing for control signals, while a separate asynchronous domain handles high-speed data payload transmission, allowing both reliability and speed requirements to be met in their respective domains
2Adaptability or versatility
If the number of nets crossing IC boundaries increases, then circuit design scalability is improved, but I/O bottleneck severity increases
Solution Approach 1:
Transactor circuits serve as intermediaries that aggregate multiple net data streams and serialize them for transmission over asynchronous links. This mediation allows the system to scale to more nets without proportionally increasing I/O bottleneck effects, as the transactors efficiently pack and transmit data
Solution Approach 2:
The patent transitions from synchronous time-division multiplexing to asynchronous spatial parallelism by introducing multiple independent data pathways through the transactor framework. This dimensional shift allows more nets to be handled simultaneously without being constrained by the sequential nature of traditional multiplexing
3Device complexity
If time division multiplexing is used for pin-muxing, then limited I/O resources are optimized, but design implementation time increases
Solution Approach 1:
Transactor circuits act as automated intermediaries that handle the complex task of data serialization and transmission timing. This automation reduces the manual partitioning and implementation time required, as the transactors systematically manage I/O resource allocation and data flow without requiring extensive manual configuration
Data Source
AI summary
A circuit design emulation system having a plurality of integrated circuits (ICs) includes a first IC. The first IC includes an originator circuit configured to issue a request of a transaction directed to a completer circuit. The request is specified in a communication protocol. The first IC includes a completer transactor circuit coupled to the originator circuit and configured to translate the request into request data. The first IC includes a first interface circuit configured to synchronize the request data from an originator clock domain to a transceiver clock domain operating at a higher frequency than the originator clock domain. The first IC includes a first transceiver circuit configured to convey the request data over a communication link that operates asynchronously to the originator clock domain.