Automated Transactor Generation for SoC Bus Verification
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Solution Overview
Problem
The manual generation of transactors for system-on-chip (SoC) bus verification is time-consuming and prone to human error, especially as the number of intellectual properties (IPs) increases, making it burdensome to effectively verify the operation of SoC buses.
Innovation Solution
A computing system equipped with a memory device and processor that automatically generates transactors based on port information extracted from design files associated with IPs, using a transactor generating tool, and verifies bus performance using these transactors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If transactors are manually generated by system testers, then transactor generation can be performed with existing tools, but the time required for transactor generation increases considerably and human error increases
Solution Approach 1:
The transactor generating tool automatically extracts port information from the IP design file and generates transactors without human intervention. The system serves itself by reading the design file, analyzing port configurations, and producing transactor code autonomously, eliminating the need for manual transactor generation by system testers.
Solution Approach 2:
The patent replaces the manual mechanical process of transactor generation with an automated computer-based system. The transactor generating tool uses software algorithms to extract port information and generate transactors, substituting the manual mechanical operations of system testers with an automated electronic system.
2Adaptability or versatility
If the number of IPs in an SoC increases, then the functionality and complexity of the electronic system improves, but the time and resources required for transactor generation and bus verification increase
Solution Approach 1:
The transactor generating tool is designed to handle multiple different IP types and bus protocols universally. It can extract port information from various IP design files and generate appropriate transactors for different bus types (AMBA AXI, AHB, APB, OCP), making the verification process efficient regardless of the number or type of IPs in the SoC.
Solution Approach 2:
The system automatically adapts to different IP configurations by extracting port information parameters from each IP's design file. Based on the extracted parameters (port names, directions, bit widths, protocols), the tool dynamically generates customized transactors, allowing efficient verification across varying SoC configurations without manual reconfiguration.
3Reliability
If manual transactor generation is used, then flexibility in transactor creation is maintained, but human error and inconsistency in transactor quality increase
Solution Approach 1:
The transactor generating tool incorporates feedback mechanisms by extracting port information from the actual IP design file and using this information to generate accurate transactors. The system reads the design file, analyzes the port configurations, and adjusts the generated transactor code to match the actual IP interface requirements, ensuring reliability and accuracy.
Data Source
AI summary
A computing system includes a memory device into which a design file for a predetermined intellectual property (IP) and a transactor generating tool are loaded, and a processor configured to execute the transactor generating tool loaded into the memory device. The transactor generating tool executed by the processor extracts port information of the IP from the design file, and generates at least one transactor corresponding to the IP based on the port information.