Transceiver Biasing for Wide-Supply IO Power-Up Protection
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Solution Overview
Problem
Designing integrated circuit (IC) IO circuits that can accommodate multiple IO standards across a wide supply range is challenging due to the low voltage limits of modern IO transistors, leading to potential system failures during power-up sequences when the supply voltage is not yet at a suitable level.
Innovation Solution
A biasing circuit that generates specific pbias and nbias voltages and a sense signal in response to the supply voltage level, allowing transceivers to operate in high-voltage or low-voltage modes, and a power-on-reset circuit that maintains the receiver output at a constant logic value during ramp-up, ensuring reliable signaling across varying voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a wide supply range is supported to accommodate multiple IO standards, then adaptability is improved, but reliability deteriorates due to transistor voltage stress
Solution Approach 1:
The patent divides the wide supply voltage range into two distinct operating modes: high-voltage mode (greater than reliability limit) and low-voltage mode (less than reliability limit). This segmentation allows the circuit to selectively activate appropriate data paths and biasing schemes for each mode, ensuring that transistors never experience voltage stress beyond their reliability limits while still supporting multiple IO standards across the full voltage range.
Solution Approach 2:
The patent implements dynamic switching between high-voltage and low-voltage data paths based on the detected supply voltage level. A biasing circuit continuously monitors the supply voltage and dynamically adjusts the operating mode and corresponding bias voltages (pbias and nbias) to match the current voltage conditions, thereby maintaining reliability across the wide supply range.
2Reliability
If voltage mode detection is implemented to switch between high-voltage and low-voltage modes, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent employs a universal biasing circuit that performs multiple functions: it detects the supply voltage level, determines the appropriate operating mode, generates the necessary bias voltages (pbias and nbias), and controls the switching between high-voltage and low-voltage data paths. This multi-functional approach consolidates what could be separate complex circuits into a single integrated unit, thereby improving reliability without proportionally increasing overall device complexity.
Solution Approach 2:
The patent introduces a sense signal as an intermediary element that carries voltage level information from the biasing circuit to the power-on-reset circuit and other voltage-mode-dependent circuits. This sense signal acts as a mediator that enables coordinated operation across different circuit blocks without requiring direct complex interconnections, thus managing system complexity while ensuring reliable voltage mode detection.
3Reliability
If power-on-reset circuit is added to force constant logic value during ramp-up, then reliability is improved, but device complexity increases
Solution Approach 1:
The power-on-reset circuit is configured to activate during the power-up ramp-up phase and force the receiver output to a constant logic value before the supply voltage reaches the reliability limit. This preliminary action prevents errant detection and system failures during the critical power-up sequence. The circuit automatically deactivates once the supply voltage stabilizes above the reliability limit, ensuring reliable operation without requiring permanent additional control logic.
Data Source
AI summary
A disclosed circuit arrangement detects the supply voltage level to the “device” (SoC, chip, SiP, etc.) and adjusts bias voltages to receiver and transmitter circuits of the device to levels suitable for the device in response to the supply voltage ramping-up during a power-on reset (“POR”) sequence. The circuitry holds the receiver output at a constant logic value while the supply voltage is ramping up and the POR signal is asserted. The disclosed circuitry also protects the transceiver as the voltage domain of the input signal is unknown and the voltage between any two terminals of a transistor of the transceiver cannot exceed a certain level.