Transceiver Clock Signal Generation Using Phase Interpolation
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Solution Overview
Problem
Integrated circuit (IC) transceivers face limitations in providing a stable and continuous system clock signal due to interruptions during resets, requiring multiple clock modules and PLLs, which increases complexity and power consumption, especially in applications where transceiver buffer configurations are bypassed or data widths differ.
Innovation Solution
A transceiver-based system that utilizes a phase interpolator and multiplexers to generate a system clock signal from existing PLLs, reducing dependency on fabric PLLs by sharing TX or RX PLLs for both data and clock paths, and employing clock buffers to ensure phase alignment and stability across multiple clock sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If transceiver PLLs are used to provide system clock signals, then the number of clock modules is reduced, but the clock signal stability and continuity are compromised due to reset interruptions
Solution Approach 1:
The system segments the clock signal path by introducing a buffer between the transceiver PLL and the system clock output. This buffer isolates the PLL from reset interruptions, allowing the PLL to continue generating stable clock signals while the transceiver undergoes reset. The buffer holds the clock signal steady during transient events, ensuring continuity.
Solution Approach 2:
The system performs preliminary action by pre-charging the buffer before the transceiver reset occurs. This ensures that when the reset interruption happens, the buffer already has the clock signal ready and can maintain output stability without interruption. The buffer is prepared in advance to handle the upcoming reset event.
2Reliability
If fabric PLLs are used to provide system clock signals, then clock signal stability is maintained, but the power consumption and device complexity increase
Solution Approach 1:
The system merges the transceiver PLL with the system clock generation function. Instead of having separate fabric PLLs dedicated to system clock generation, the transceiver PLL is configured to serve dual purposes: providing clock signals to the transceiver and simultaneously providing the system clock signal to the fabric. This consolidation eliminates redundant PLL circuits and reduces overall power consumption.
Solution Approach 2:
The transceiver PLL is designed with multi-functionality to serve both the transceiver data path and the system clock distribution. By configuring the PLL output to feed both the transceiver input and the system clock buffer, a single component performs multiple functions that previously required separate dedicated circuits, thereby reducing power consumption and device complexity.
3Adaptability or versatility
If transceiver buffer is bypassed, then data width flexibility is improved, but the phase interpolator rotation prevents clock signal usability
Solution Approach 1:
The system introduces a buffer as an intermediary component between the phase interpolator and the system clock output. When the transceiver buffer is bypassed for data width flexibility, this intermediary buffer captures the potentially rotated clock signal from the phase interpolator, stabilizes it, and provides a clean, non-rotated system clock signal to the fabric. The buffer mediates between the flexible data path and the stable clock requirement.
Data Source
AI summary
An apparatus relating generally to a transmitter-side of a transceiver or a transmitter used to provide a clock signal is disclosed. In this apparatus, a first signal source is to provide a first periodic signal. A second signal source is to provide a second periodic signal. A first multiplexer is coupled to receive the first periodic signal and the second periodic signal to provide a selected one thereof as a first selected output. A phase interpolator is coupled to the first multiplexer to receive the first selected output. The phase interpolator includes a second multiplexer. The second multiplexer is coupled to receive the first selected output and a phase-interpolated version of the first selected output to output a selected one thereof as a second selected output. A divider is coupled to the second multiplexer to receive the second selected output to provide the clock signal.