Transceiver LO Duty-Cycle Tuning for Half-Clock Spur Reduction
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Solution Overview
Problem
In wireless communication systems, particularly in 4G and 5G transceivers with inter-band carrier aggregation, undesirable frequency spurs at half the carrier frequency can degrade the receiver's signal-to-noise ratio and de-sense the receiver, necessitating a reduction in half clock spur levels to minimize impact.
Innovation Solution
A transceiver system comprising a duty cycle controller, frequency synthesizer, transmitter, measurement receiver, and power measurer, which generates and controls the duty cycle of local oscillator signals to minimize spurs by determining an optimum duty cycle control code through calibration, using polynomial regression to adjust the voltage controlled oscillator's duty cycle for reduced spur levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the VCO frequency is kept low to reduce power consumption and design complexity, then power consumption and design complexity are reduced, but an undesirable spur appears at half the carrier frequency that de-senses the receiver
Solution Approach 1:
The patent adjusts the duty cycle of the VCO output signal as a parameter change to minimize the half clock spur. By varying the duty cycle from its default 50% value, the spur level at half the carrier frequency is reduced, allowing the VCO to operate at lower frequencies without causing receiver de-sensing. This resolves the contradiction by modifying a controllable parameter (duty cycle) to eliminate the harmful effect while maintaining the beneficial low-frequency operation.
2Device complexity
If the VCO frequency is kept low to simplify design, then design complexity is reduced, but the half clock spur lands within the receiver frequency and de-senses the receiver
Solution Approach 1:
The patent modifies the duty cycle parameter of the VCO output to minimize spur levels at half the carrier frequency. This allows the system to maintain simple low-frequency VCO design while actively controlling the duty cycle to prevent the harmful half clock spur from landing in the receiver band, thus resolving the contradiction between design simplicity and receiver performance.
Solution Approach 2:
The patent implements a feedback mechanism where the measured spur level at half the carrier frequency is used to adjust the duty cycle control code. The system iteratively refines the duty cycle to minimize the spur, providing automatic compensation that maintains receiver performance without increasing overall system complexity.
3Object-affected harmful factors
If the duty cycle is adjusted to minimize spurs, then spur levels are reduced, but additional calibration and control mechanisms are required
Solution Approach 1:
The patent implements a self-calibrating mechanism where the system automatically measures its own spur levels and adjusts the duty cycle accordingly. The measurement receiver detects spurs, and the controller autonomously refines the duty cycle control code without requiring external intervention, thereby minimizing spur levels while adding only minimal control complexity.
Solution Approach 2:
A feedback loop is established where spur measurements from the measurement receiver are fed back to the controller, which adjusts the duty cycle to minimize spurs. This closed-loop control automatically optimizes spur reduction while maintaining manageable system complexity through intelligent control algorithms.
4Measurement precision
If polynomial regression is used to determine optimal duty cycle, then measurement precision is improved, but computational complexity increases
Solution Approach 1:
The patent applies polynomial regression, which may be more computationally intensive than necessary, to accurately determine the optimal duty cycle control code. This excessive action in terms of computational effort yields high measurement precision in spur level characterization, allowing the system to find the optimal duty cycle setting with greater accuracy, thereby resolving the contradiction between precision and complexity.
Data Source
AI summary
A method includes producing a plurality of TX LO signals by a first LO generator comprising a first frequency doubler and a first frequency divider, the first frequency doubler configured to receive a VCO signal having a first frequency and generate a first signal fed into the first frequency divider, the first signal having a second frequency that is twice the first frequency, producing a plurality of MRX LO signals by a second LO generator comprising a second frequency doubler and a second frequency divider, the second frequency doubler configured to receive the VCO signal and generate a second signal fed into the second frequency divider, the second signal having the second frequency, configuring the TX to operate at a first LO frequency equal to the second frequency, and configuring the MRX to operate at a second LO frequency equal to the first frequency through disabling the second frequency doubler.