Transceiver Loopback Test Circuit With Selective Scan Registers
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Solution Overview
Problem
Scannable flip-flop registers used for testing digital circuitry consume more area, power, and are slower than non-scannable flip-flop registers, while non-scannable registers are not suitable for effective testing due to lack of visibility and longer test time.
Innovation Solution
Implementing scannable flip-flop registers for low-frequency digital circuits and non-scannable flip-flop registers for high-frequency circuits, allowing for efficient testing by loading test patterns at low frequencies and operating at high frequencies during normal operation, with loopback paths for data comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scannable flip-flop registers are used for testing digital circuitry, then fault coverage and test effectiveness are improved, but area consumption, power consumption increase and operating speed decreases
Solution Approach 1:
The patent applies local quality by making only the necessary registers scannable (launch register and receive register) while keeping other registers non-scannable. This selective approach provides the required test effectiveness at the specific locations where visibility and control are needed, while minimizing the area and power overhead associated with scannable register structures throughout the entire circuit.
Solution Approach 2:
The patent segments the register structures into different types (scannable and non-scannable) based on their functional requirements in the testing process. The launch and receive registers are segmented as scannable for test purposes, while other registers are kept as standard non-scannable flip-flops, thereby achieving test effectiveness without universally increasing area and power consumption across all registers.
2Reliability
If scannable flip-flop registers are used for testing digital circuitry, then fault coverage and test effectiveness are improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by making only the necessary registers scannable (launch register and receive register) while keeping other registers non-scannable. This selective approach provides the required test effectiveness at the specific locations where visibility and control are needed, while minimizing the area and power overhead associated with scannable register structures throughout the entire circuit.
3Reliability
If scannable flip-flop registers are used for testing digital circuitry, then fault coverage and test effectiveness are improved, but operating speed decreases
Solution Approach 1:
The patent applies local quality by making only the necessary registers scannable (launch register and receive register) while keeping other registers non-scannable. This selective approach provides the required test effectiveness at the specific locations where visibility and control are needed, while minimizing the area and power overhead associated with scannable register structures throughout the entire circuit.
Solution Approach 2:
The patent applies dynamics by enabling the circuit to operate in different modes (test mode and normal operation mode) with different register configurations. During test mode, the launch and receive registers operate as scannable registers for fault detection. During normal operation, these same registers function as standard high-speed flip-flops, thereby maintaining operating speed while achieving test effectiveness when needed.
4Speed
If non-scannable flip-flop registers are used for high-frequency circuits, then operating speed and area efficiency are improved, but test effectiveness decreases and test time increases
Solution Approach 1:
The patent applies dynamics by enabling the circuit to operate in different modes (test mode and normal operation mode) with different register configurations. During test mode, the launch and receive registers operate as scannable registers for fault detection. During normal operation, these same registers function as standard high-speed flip-flops, thereby maintaining operating speed while achieving test effectiveness when needed.
Data Source
AI summary
A transceiver circuit is disclosed, the transceiver circuit including a first register circuit, configured to receive serial stimulus data and to generate multi-bit parallel stimulus data, a serializer circuit configured to receive the multi-bit parallel stimulus data and to generate serialized data based on the multi-bit parallel stimulus data, where the serializer circuit includes a serializer data storage device, and where the serializer data storage device lacks circuit structures for scanability, a deserializer circuit configured to receive serial receiver data corresponding with the serialized data and to generate multi-bit parallel response data based on the serial receiver data, where the deserializer circuit includes a deserializer data storage device, and where the deserializer data storage device lacks circuit structures for scanability, and a second register circuit, configured to receive the multi-bit parallel response data and to generate serial response data.