Wireless Transceiver Memory Sharing Circuit

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Solution Overview

Problem

Existing wireless networking transceiver systems, such as Bluetooth and Wi-Fi transceivers, often require significant memory allocations even when only a subset of features are needed, leading to wasted memory and inefficiency, especially when future upgrades are anticipated.

Innovation Solution

The implementation of memory-sharing circuitry among wireless networking transceiver subsystems, allowing each subsystem to dynamically allocate and share memory based on the specific requirements of its protocol features, using multiplexer and demultiplexer circuits to facilitate memory access across multiple banks, thereby optimizing memory usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If each transceiver subsystem is provided with sufficient memory for the largest possible feature set, then the system can support future upgrades and full feature sets, but this results in wasted unused memory when only a subset of features is implemented

Engineering Contradiction:

Improvesupport for future upgrades and full feature setsVSAvoidwasted unused memory

Core Design Contradiction:

Adaptability or versatilityVSLoss of substance

Solution Approach 1:

Multiple transceiver subsystems share a common memory resource through memory-sharing circuitry. The memory is physically distributed among subsystems but logically shared, allowing dynamic allocation based on actual feature requirements rather than provisioning for maximum capacity in each subsystem

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The memory allocation is made dynamic through multiplexer circuitry that can reconfigure which memory banks are accessible to which transceiver subsystems based on runtime requirements. This allows the system to adapt memory distribution to match actual feature usage rather than being static

Inventive Principle:

Principle #15Dynamics

2Adaptability or versatility

If extra memory is provided against the possibility of future upgrades, then the system can accommodate future feature expansions, but this results in even more potentially wasted memory in current implementations

Engineering Contradiction:

Improveaccommodation of future feature expansionsVSAvoidpotentially wasted memory

Core Design Contradiction:

Adaptability or versatilityVSLoss of substance

Solution Approach 1:

The system prepares memory resources in advance by provisioning a shared memory pool that can accommodate future upgrades, but this memory is not allocated to any specific subsystem until needed. The memory-sharing infrastructure is established beforehand, allowing flexible future expansion without current waste

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The shared memory serves multiple transceiver subsystems simultaneously and can be dynamically allocated to support different feature sets across different subsystems. A single memory resource performs the function of supporting multiple potential future configurations

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Ease of operation

If each transceiver subsystem has independent memory for its protocol features, then each subsystem can operate autonomously, but this increases total memory requirements when multiple subsystems are instantiated

Engineering Contradiction:

Improveautonomous operation of each subsystemVSAvoidtotal memory requirements

Core Design Contradiction:

Ease of operationVSQuantity of substance

Solution Approach 1:

Memory-sharing circuitry including multiplexers acts as an intermediary between transceiver subsystems and the physical memory banks. This intermediary layer allows subsystems to access memory autonomously through standardized interfaces while the underlying memory is shared, decoupling operational independence from physical memory allocation

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10972142B1Wireless networking transceiver system with shared memory

Publication Date: 2021.04.06 NXP USA INC

AI summary

Wireless networking transceiver circuitry for an integrated circuit device includes a plurality of wireless networking transceiver subsystems, each subsystem including respective processing circuitry configurable for coupling to radio circuitry to implement a respective set of protocol features selected from at least one overall set of protocol features. Memory circuitry is provided, sufficient to support a respective set of protocol features in each subsystem when at least one respective set of protocol features is smaller than the overall set of protocol features. Memory-sharing circuitry is provided, configurable to couple respective portions of the memory circuitry to the processing circuitry of respective subsystems. The memory circuitry and the memory-sharing circuitry may be outside the subsystems, or distributed within the subsystems. The memory may be 60% of an amount of memory sufficient to support the overall set of protocol features in all subsystems. Each processing circuit may be coupled to radio circuitry.