Transceiver Linearity Compensation via On-Chip Feedback Loop
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Solution Overview
Problem
Conventional wireless communication systems face challenges in maintaining linearity of power amplifiers, especially in compact mobile devices, due to the need for costly and impractical off-chip feedback paths for linearity compensation, which are not suitable for portable devices and are affected by environmental changes.
Innovation Solution
The implementation of an on-chip closed loop using existing components on a transceiver IC chip, including a power amplifier, attenuator, and digital signal processor, to establish a cost-effective linearity compensation mechanism that pre-distorts signals and compensates for nonlinearity, eliminating the need for off-chip components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an off-chip feedback path is built for linearity compensation, then linearity is improved, but device cost and complexity increase
Solution Approach 1:
The patent merges the feedback path into the existing on-chip infrastructure by routing the power amplifier output through the receiver chain and analog-to-digital converter back to the digital signal processor. This combines multiple functions (power amplification, reception, conversion, and processing) into a unified on-chip closed loop, eliminating the need for separate off-chip feedback components while maintaining linearity compensation capability
Solution Approach 2:
The patent makes existing on-chip components serve multiple functions. The receiver chain and analog-to-digital converter, originally designed for signal reception, are also utilized for feedback signal acquisition in the linearity compensation loop. The digital signal processor handles both normal signal processing and linearity compensation algorithms, reducing the need for dedicated feedback path components
2Reliability
If an off-chip feedback path is built for linearity compensation, then linearity is improved, but device size increases
Solution Approach 1:
The patent merges the feedback path into the existing on-chip infrastructure by routing the power amplifier output through the receiver chain and analog-to-digital converter back to the digital signal processor. This combines multiple functions (power amplification, reception, conversion, and processing) into a unified on-chip closed loop, eliminating the need for separate off-chip feedback components while maintaining linearity compensation capability
Solution Approach 2:
The patent implements nesting by placing the feedback loop structure within the existing transceiver chip architecture. The feedback path is nested within the on-chip signal processing chain, utilizing the receiver and converter circuits that already exist on the chip, thereby avoiding additional external components and reducing overall device volume
3Reliability
If conventional off-chip feedback is used, then linearity compensation is achieved, but cost increases
Solution Approach 1:
The patent merges the feedback path into the existing on-chip infrastructure by routing the power amplifier output through the receiver chain and analog-to-digital converter back to the digital signal processor. This combines multiple functions (power amplification, reception, conversion, and processing) into a unified on-chip closed loop, eliminating the need for separate off-chip feedback components while maintaining linearity compensation capability
Solution Approach 2:
The patent implements self-service by enabling the transceiver to perform its own linearity compensation using internally available resources. The system utilizes its own receiver chain, analog-to-digital converter, and digital signal processor to monitor and compensate for power amplifier nonlinearity, eliminating the need for external feedback components and reducing manufacturing cost
Data Source
AI summary
One embodiment of the present invention provides a transceiver for wireless communication. The transceiver includes a transmitting circuit, a receiving circuit, a power amplifier coupled to the transmitting circuit, and a looping mechanism configured to establish a closed loop that couples an output of the power amplifier to an input of the receiving circuit in response to a linearity compensation need, thereby facilitating cost-effective linearity compensation.


