Transceiver Sampling Timing Generator for Asynchronous Clock Synchronization
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Solution Overview
Problem
In communication systems using buses like CAN and LIN, transceivers often misrecognize signal levels due to asynchronous operation between signal processors and transceivers, leading to incorrect sampling of data signals, especially when using simple oscillators for clock generation, which can result in misalignment of sampling points within bit durations.
Innovation Solution
A transceiver design that includes a clock generator to synchronize a second clock with the signal processor's clock, a sampling timing generator to detect start data and generate sampling timings spaced according to the second clock's period, ensuring proper sampling of data signal bits by maintaining an interval between level transitions and sampling timings, thus reducing misrecognition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a simple oscillator is used for clock generation to reduce cost and power consumption, then device complexity and power consumption are reduced, but clock frequency accuracy deteriorates causing sampling misalignment
Solution Approach 1:
The patent introduces a sampling timing generator as an intermediary component between the simple oscillator and the data sampling process. This mediator generates precise sampling timings by counting clock cycles and using lookup tables to determine optimal sampling moments, thereby achieving accurate sampling without requiring a complex or high-accuracy oscillator.
Solution Approach 2:
The patent performs preliminary actions by pre-calculating and storing sampling timing information in lookup tables during system initialization. The sampling timing generator uses these pre-computed tables to determine optimal sampling moments without requiring real-time complex calculations, thus maintaining simplicity while ensuring accuracy.
2Adaptability or versatility
If the signal processor operates on its own clock different from the bus clock, then operational independence is maintained, but data sampling accuracy deteriorates due to asynchronous operation
Solution Approach 1:
The patent implements feedback mechanisms where the sampling timing generator continuously monitors the relationship between the signal processor's clock and the bus clock. It uses this feedback to dynamically adjust sampling timings through cycle counting and lookup table references, ensuring accurate sampling despite asynchronous operation and maintaining operational independence.
3Measurement precision
If sampling is performed at the midpoint of bit duration for optimal accuracy, then data recognition accuracy is improved, but timing sensitivity increases making the system more vulnerable to clock drift
Solution Approach 1:
The patent makes the sampling timing dynamic rather than fixed. The sampling timing generator continuously adjusts sampling moments based on real-time clock cycle counting and the current state of the transmission data signal. This dynamic adaptation allows the system to maintain optimal sampling accuracy while compensating for clock drift and variations, thereby improving reliability.
Data Source
AI summary
In a transceiver, a clock generator generates a second clock synchronized with a first clock. The second clock has a period corresponding to a duration of one bit of a digital signal. When first transmission data is supplied to the transceiver with being asynchronous to the second clock, a sampling timing generator detects start data of the first transmission data as a start timing, and generates sampling timings based on the first clock in response to the start timing. The sampling timings have intervals each of which is defined to correspond to the period of the second clock. The first sampling timing is spaced from the start timing. A sampling module samples, at each of the sampling timings, the first transmission data, thus generating second transmission data synchronized with the second clock.