Transceiver Clock Training Without a Separate MIPI Clock Line
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Solution Overview
Problem
The use of a clock line for internal communication in display devices using the MIPI protocol increases physical and spatial costs and power consumption.
Innovation Solution
A transceiver with a transmitter and receiver connected through multiple lines, employing variable clock training patterns and voltage ranges in different modes to optimize locking time and prevent electromagnetic interference, while eliminating the need for a separate clock line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate clock line is used for internal communication in display devices using the MIPI protocol, then clock synchronization is improved, but physical and spatial costs increase and power consumption increases
Solution Approach 1:
The patent combines the clock signal and data signals into a single transmission line, eliminating the need for a separate clock line. The transmitter encodes clock information within the data stream, and the receiver extracts the clock signal from the combined transmission, thereby reducing physical space and spatial costs while maintaining clock synchronization.
Solution Approach 2:
The transmission line is designed to serve multiple functions simultaneously: it transmits both data signals and clock signals, and carries both information data and synchronization timing. This multi-functionality eliminates the need for dedicated separate lines for each signal type, reducing overall physical and spatial requirements.
2Reliability
If a separate clock line is used for internal communication in display devices using the MIPI protocol, then clock synchronization is improved, but power consumption increases
Solution Approach 1:
By merging clock and data transmissions into a single line, the patent reduces the total number of active transmission lines, thereby reducing overall power consumption. The receiver uses the data signal itself to generate the clock signal, eliminating the need for a separate power-intensive clock line.
Solution Approach 2:
The receiver extracts and generates the clock signal from the incoming data signal itself, making the system self-sufficient for clock generation. This eliminates the need for a separate clock line that would require additional power, as the clock is derived from the data transmission rather than requiring an independent power-intensive transmission path.
3Measurement precision
If the clock training pattern length is increased to improve locking time, then clock synchronization accuracy is improved, but electromagnetic interference increases
Solution Approach 1:
The patent dynamically adjusts the clock training pattern length based on the driving mode. In non-burst modes where continuous transmission occurs, shorter training patterns are used to minimize electromagnetic interference. In burst modes where transmission is intermittent, longer training patterns can be employed to achieve accurate locking without excessive interference, as the system has time to settle between bursts.
Solution Approach 2:
The patent changes the parameter of clock training pattern length according to different driving modes. By selecting appropriate pattern lengths based on whether the system is in burst or non-burst mode, the patent optimizes the balance between achieving sufficient locking time for accurate synchronization and minimizing electromagnetic interference generated by prolonged high-frequency signaling.
Data Source
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AI summary
A transceiver (TSCV) includes a transmitter (TXD) and a receiver (RXD) which are connected to each other through a first line (dp1) and a second line (dn1). The transmitter (TXD) transmits a first clock training pattern (CLK-T1) to the receiver (RXD) in a first period (P1, P1', P1"), transmits a second clock training pattern (CLK-T2) and a first first payload (ePayload_1) to the receiver (RXD) in a second period (P2, P2', P2"), and transmits a third clock training pattern (CLK-T3) and a second first payload (ePayload_2) to the receiver in a third period (P3, P3', P3"). The first clock training pattern (CLK-T1), the second clock training pattern (CLK-T2), and the third clock training pattern (CLK-T3) are variable based on a plurality of driving modes (DRM1, DRM2, DRM3, DRM4).