Half-Duplex Transceiver Power Management via Snooze Mode

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Half-duplex transceivers experience unnecessary power consumption due to continuous power supply to transmitter subsystem components during reception phases, as switching between transmission and reception modes is hindered by the high settling time of DC-DC converters, which is longer than the turn-around time between subsystems.

Innovation Solution

A power management circuit with a snooze mode controller is introduced to configure the DC-DC converter into various snooze control modes, allowing the switching circuit and driver circuit to remain in an OFF-state during inactive periods, reducing power consumption by selectively snoozing the converter based on transceiver operating inputs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the DC-DC converter is continuously powered during reception phase, then the transmitter subsystem components are ready for immediate transmission, but unnecessary power consumption occurs

Engineering Contradiction:
Improvetransition speed between transmission and receptionVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The DC-DC converter is kept in a low-power standby mode during reception phase rather than being completely shut down, maintaining minimal readiness for quick transition to transmission mode while consuming significantly less power than continuous operation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements periodic monitoring and dynamic switching between power states, adjusting the DC-DC converter's operation based on actual transmission needs and channel conditions, allowing it to alternate between active and low-power states

Inventive Principle:
Principle #19Periodic action

2Use of energy by moving object

If the DC-DC converter is switched OFF during reception phase, then power consumption is reduced, but the settling time exceeds the turn-around time between subsystems

Engineering Contradiction:
Improvepower consumptionVSAvoidtransition time
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The DC-DC converter is placed in a preliminary low-power standby state during reception that maintains essential circuit readiness, enabling fast wake-up and transition to full transmission mode without requiring complete re-initialization, thus meeting the tight turn-around time requirements

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts the DC-DC converter's power state based on real-time operational requirements, implementing multiple power modes (fully active, standby, and off) that can be switched according to the specific transition needs between transmission and reception phases

Inventive Principle:
Principle #15Dynamics

3Use of energy by moving object

If the DC-DC converter toggles between PWM mode and PFM mode, then battery current is saved, but the switching time between modes is significantly greater than the turn-around time and increases circuit complexity

Engineering Contradiction:
Improvebattery currentVSAvoidcircuit elements
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

A unified power management controller is designed that can operate the DC-DC converter in multiple modes (PWM, PFM, and standby) using a single integrated circuit architecture, eliminating the need for separate dedicated circuits for each mode and reducing overall system complexity while maintaining energy-saving capabilities

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9756572B2Reduction of power consumption in a half-duplex transceiver
Publication Date: 2017.09.05 TEXAS INSTRUMENTS INC
  • US9756572B2 patent drawing
  • US9756572B2 patent drawing
  • US9756572B2 patent drawing

AI summary

Circuits and methods for reducing power consumption in a half-duplex transceiver are disclosed. In an embodiment, a power management circuit of half-duplex transceiver includes direct current to direct current (DC-DC) converter and snooze mode controller. The DC-DC converter includes switching circuit and driver circuit to drive the switching circuit. The DC-DC converter provides power supply to at least one element of a transmitter sub-system of the half-duplex transceiver, and operates in snooze control modes. The snooze mode controller is coupled to the DC-DC converter and configured to generate a control signal based on at least one transceiver operating input, where the control signal causes the DC-DC converter to operate in one of the snooze control modes, the snooze control modes corresponding to snooze duty cycles and where in each snooze control mode, the switching circuit and the driver circuit remain in an OFF-state based on a respective snooze duty cycle.