Electrical Transceiver Timing Control for Synchronous Ethernet

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Commercialized electrical transceivers cannot support synchronous Ethernet in master mode and experience time synchronization errors due to mismatched signal delays when operating between IEEE 1588 nodes over copper cables.

Innovation Solution

An electrical transceiver design that includes a processor with a timing control unit to match the time delays of transmission and reception signals by controlling buffering speeds, ensuring equal delays in both directions through a delay control unit, and utilizing PLLs for clock signal extraction and transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If electrical transceivers operate in master mode to transmit and receive synchronous signals, then synchronous Ethernet functionality is enabled, but time synchronization errors occur due to mismatched transmission and reception delays

Engineering Contradiction:

Improvesynchronous Ethernet master mode supportVSAvoidtime synchronization accuracy

Core Design Contradiction:

Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent pre-calculates and pre-configures delay compensation values for transmission and reception paths before actual synchronous Ethernet operation. The delay compensation unit is prepared with predetermined delay values that are applied to balance the timing of transmitted and received packets, preventing time synchronization errors before they occur.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent dynamically adjusts delay compensation parameters based on measured transmission and reception delay differences. The delay compensation unit modifies timing parameters in real-time to equalize the delays in both directions, ensuring accurate time synchronization while maintaining master mode functionality.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If electrical transceivers use copper cables for serial links, then facility costs are reduced compared to optical interfaces, but signal delay matching between transmission and reception becomes more difficult

Engineering Contradiction:

Improvetime synchronization reliabilityVSAvoiddelay matching complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a delay compensation unit as an intermediary component between the physical layer transceiver and the higher-layer processing. This mediator measures the actual delays in transmission and reception paths through copper cables and applies compensatory delay adjustments, simplifying the overall delay matching process while maintaining synchronization reliability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements a feedback mechanism where the delay compensation unit continuously monitors the timing differences between transmitted and received packets over copper cables. Based on this feedback, the system automatically adjusts delay compensation values to maintain equal delays in both directions, reducing the complexity of manual delay matching while ensuring reliable time synchronization.

Inventive Principle:

Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables synchronous Ethernet operation in both master and slave modes without time synchronization errors, supporting IEEE 1588 precision time protocol and reducing facility and operational costs by eliminating the need for separate optical interfaces.

Implementation Method 1

a first PLL transmitting a transmission clock signal extracted from the signal transmitted from the host to the optical physical layer (PHY) transceiver

Methodology Applied

Scientific EffectPhase Locked Loop (PLL):

Implementation Method 2

a second PLL transmitting a received clock signal extracted from the signal transmitted from the serial link to the encoding unit

Methodology Applied

Scientific EffectPhase Locked Loop (PLL):

Data Source

PatentUS9942025B2Electrical transceiver for synchronous ethernet

Publication Date: 2018.04.10 SOLUTIONS SARL

AI summary

Disclosed is an electrical transceiver for synchronous Ethernet, including: a first interface connected with a host; a second interface including a physical layer (PHY) transceiver connected with a serial link; and a processor connected with the first interface and the second interface, wherein the processor includes a timing control unit controlling a transmission signal transmitted to the second interface from the first interface and a reception signal transmitted to the first interface from the second interface to have the same time delay.