Transcendental Calculation Unit for IEEE 754-2008 Accuracy
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Solution Overview
Problem
Current transcendental function evaluation in integrated circuits is inefficient due to high time consumption in argument reduction and high precision multiplication, particularly in software implementations, which hinders achieving IEEE 754-2008 accuracy with smaller hardware footprints.
Innovation Solution
A processor with a Floating Point Transcendental Calculation Unit comprising a Configuration Table, Power Series Multiplier, Coefficient Series Multiplier and Accumulator, Round and Normalize Stage, and Control Circuit, which iteratively develops power series and accumulates products to efficiently evaluate transcendental functions, reducing the need for large tables and improving precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If software implementations are used for transcendental function evaluation, then flexibility and ease of implementation are improved, but time consumption increases significantly
Solution Approach 1:
The patent replaces software-based transcendental function evaluation with a dedicated hardware circuit implementation. The hardware circuit includes argument reduction units, polynomial evaluation units, and lookup tables that work together to compute transcendental functions directly in hardware, eliminating the time-consuming software execution while maintaining implementation flexibility through configurable circuit design.
Solution Approach 2:
The hardware circuit is divided into multiple functional segments: argument reduction units that preprocess input values, polynomial evaluation units that compute intermediate results, and lookup tables that store precomputed coefficients. This segmentation allows each unit to be optimized independently while working together to achieve fast overall computation.
2Measurement precision
If hardware circuits are designed for high precision transcendental calculation, then accuracy is improved, but hardware footprint increases
Solution Approach 1:
The patent applies partial precision strategies where different parts of the calculation use different precision levels. Lookup tables store coefficients at high precision, but intermediate calculations use sufficient but not excessive precision. This approach achieves IEEE 754-2008 accuracy requirements while avoiding the hardware overhead of maintaining full precision throughout all calculation stages.
Solution Approach 2:
The circuit performs argument reduction as a preliminary step before polynomial evaluation. By reducing the input argument to a standardized range first, the subsequent polynomial evaluation can use smaller, more compact lookup tables and simpler computation units, thereby reducing overall hardware footprint while maintaining accuracy.
3Measurement precision
If argument reduction and high precision multiplication are performed extensively, then IEEE 754-2008 accuracy is achieved, but time consumption increases
Solution Approach 1:
The hardware circuit implements continuous pipelined operation where argument reduction, polynomial evaluation, and result generation occur in overlapping time periods. Multiple calculation stages work simultaneously on different data, maintaining continuous useful action that achieves high precision results without the sequential time delays that would occur in software implementations.
Solution Approach 2:
The patent introduces intermediate lookup tables that store precomputed polynomial coefficients and correction terms. These intermediaries allow the circuit to achieve high precision results by combining approximate calculations with precomputed correction values, avoiding the need for extensive real-time high precision multiplication while maintaining IEEE 754-2008 accuracy.
Data Source
AI summary
A transcendental calculation unit includes a configuration table storing a set of constants and provide a selected one of the constants, a power series multiplier that iteratively develops a power series, a coefficient series multiplier and accumulator that develops an accumulated product of the power series and the constant, and a round and normalize stage that rounds the accumulated product and normalizes rounded product.