Transfer Processing Device Buffer Circuit Timing Synchronization

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Solution Overview

Problem

The transfer processing of arithmetic instructions in virtual computers can lead to erroneous transfers due to timing deviations between software processing and transfer processing, particularly when software processing is slower than the transfer processing circuit.

Innovation Solution

A transfer processing device is designed with an arithmetic instruction number acquisition circuit, a buffer circuit, a transfer information acquisition circuit, and a software processing unit. The buffer circuit holds the arithmetic instruction and its number until software processing is completed, ensuring synchronized transfer processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If software processing is used for transfer processing circuit, then flexibility and adaptability are improved, but processing speed deteriorates

Engineering Contradiction:

Improveflexibility of transfer processingVSAvoidprocessing speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The system divides transfer processing into two segments: high-speed hardware transfer processing circuit and flexible software processing unit. The hardware circuit handles time-critical transfer operations while the software unit manages table updates and error recovery, allowing each segment to operate at its optimal speed without interfering with the other.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A buffer circuit is introduced as an intermediary component between the software processing unit and the transfer processing circuit. This buffer absorbs timing deviations by temporarily storing transfer information, allowing the fast hardware circuit to continue operating while the slower software unit processes table updates without causing errors.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Speed

If high-speed transfer processing is implemented, then transfer speed is improved, but timing synchronization with software processing deteriorates

Engineering Contradiction:

Improvetransfer speedVSAvoidtiming synchronization

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The software processing unit performs table updates and error recovery operations in advance or in parallel with the transfer processing. By preparing transfer information tables beforehand and using error detection/correction codes预先, the system ensures that high-speed transfer operations can proceed without waiting for software processing to complete, maintaining both speed and synchronization.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system implements error detection and correction mechanisms that provide feedback between the hardware transfer circuit and software processing unit. Error detection codes monitor transfer operations, and when errors are detected, the software unit corrects them and notifies the hardware circuit, ensuring timing synchronization and reliability without significantly impacting transfer speed.

Inventive Principle:

Principle #23Feedback

3Adaptability or versatility

If software processing is slower than transfer processing, then adaptability is improved, but transfer accuracy deteriorates

Engineering Contradiction:

Improvesoftware processing capabilityVSAvoidtransfer accuracy

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The system prepares error correction codes and backup transfer information in advance, creating a cushion that compensates for the speed difference between software and hardware processing. When transfer errors occur, pre-prepared correction mechanisms immediately compensate without requiring slow software intervention, maintaining transfer accuracy while preserving software adaptability.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The system replaces reliance on slow software processing for error correction with hardware-based error detection and correction codes. This substitution allows error handling to occur at hardware speed, matching the transfer processing speed and maintaining accuracy, while software retains its adaptive role in managing complex transfer scenarios.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS12210410B2Transfer processing device

Publication Date: 2025.01.28 NIPPON TELEGRAPH & TELEPHONE CORP

AI summary

A transfer processing device includes an arithmetic instruction number acquisition circuit, a buffer circuit, a transfer information acquisition circuit, and a software processing unit. The arithmetic instruction number acquisition circuit acquires a transfer instruction number corresponding to transfer information which is information related to the next transfer destination of an arithmetic instruction. The buffer circuit is arranged between the arithmetic instruction number acquisition circuit and the transfer information acquisition circuit, and temporarily stores and relays the arithmetic instruction and the arithmetic instruction number supplied from the arithmetic instruction number acquisition circuit to the transfer information acquisition circuit. The transfer information acquisition circuit acquires transfer information on the basis of the arithmetic instruction number, and gives the acquired transfer information to the arithmetic instruction. The buffer circuit holds the arithmetic instruction number and the arithmetic instruction until an output request from the transfer information acquisition circuit is received.