Transfer Circuit Stabilizer for Shift Register Potential Rise

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Solution Overview

Problem

Conventional shift register circuits can experience undesired potential rises in output signals, leading to potential accumulation and malfunction when connected in series, particularly with depletion-type transistors having negative threshold voltages.

Innovation Solution

A transfer circuit design incorporating an input circuit, reset circuit, output circuit, and output stabilizer circuit, including an inverter circuit that prevents significant potential rises by using transistors and capacitors to synchronize signal transfer with clock signals, ensuring the transistor T1 remains in the OFF state and inhibiting output terminal potential increases.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional register circuit or simple two-phase drive transfer circuit is used, then the circuit structure remains simple, but an undesired potential rise occurs in the output signal leading to accumulation and malfunction

Engineering Contradiction:
Improvesignal transfer reliabilityVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The transfer circuit is divided into multiple functional blocks: input circuit (transistor T3, capacitor C3), reset circuit (transistor T4, capacitor C4), output circuit (transistor T1, capacitor C1), and output stabilizer circuit (transistor T2, capacitor C2). This segmentation allows each block to perform a specific function, with the output stabilizer circuit specifically designed to prevent potential rise accumulation while maintaining overall circuit reliability.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If depletion-type transistors with negative threshold voltage are used, then the transistor can operate with simplified biasing, but significant potential rise occurs at the output terminal causing erroneous transfer

Engineering Contradiction:
Improvetransistor biasing simplicityVSAvoidsignal transfer accuracy
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The output stabilizer circuit (transistor T2, capacitor C2) is configured to preemptively counteract the potential rise effect before it can cause erroneous signal transfer. When the output signal is at low level, the stabilizer circuit actively maintains the output terminal potential, preventing the accumulation effect that would otherwise lead to malfunction in subsequent stages.

Inventive Principle:
Principle #9Preliminary anti-action

3Productivity

If repeated transfer of control signal through series-connected transfer circuits is performed, then the control signal can be distributed to multiple rows, but potential rise accumulates leading to malfunction

Engineering Contradiction:
Improvesignal distribution capabilityVSAvoidsignal integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The output stabilizer circuit functions as a feedback mechanism that continuously monitors and corrects the output terminal potential. By feeding back control signals to maintain the potential at appropriate levels, the circuit prevents accumulation of potential rise across multiple series-connected stages, ensuring signal integrity is maintained throughout the shift register.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10770003B2Transfer circuit, shift register, gate driver, display panel, and flexible substrate
Publication Date: 2020.09.08 MAGNOLIA BLUE CORP
  • US10770003B2 patent drawing
  • US10770003B2 patent drawing
  • US10770003B2 patent drawing

AI summary

A transfer circuit includes an input circuit, a reset circuit, an output circuit, and an output stabilizer circuit, and obtains an input signal at an input terminal, holds the input signal, and outputs the input signal from an output terminal as an output signal in synchronization with a clock signal. The transfer circuit includes an inverter circuit that has an input terminal connected to at least one of the input and output terminals of the transfer circuit, and outputs, from an output terminal, an inverted signal having an inverted polarity of at least one of the input and output signals. The reset circuit includes a first transistor having a control signal end connected to the output terminal of the inverter circuit, the first transistor switching continuity and discontinuity of a signal path between one end of a first capacitor that holds the input signal and a first power supply.