Transfer-Printed Precision Devices Using Wafer Test Structure Mapping
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Solution Overview
Problem
The challenge lies in creating small, high-precision devices such as resistors for integrated circuits, as existing photolithographic methods result in variable performance due to material deposition limitations, making it difficult to integrate high-precision components of millimeter or sub-micron sizes into electronic circuits without significant area usage and performance variability.
Innovation Solution
The solution involves a device source wafer with test structures to measure device characteristics, allowing for micro-transfer printing of high-precision devices onto a target substrate, enabling precise placement and connection of devices like resistors, capacitors, or transistors with characteristics known to within 0.001% accuracy, without increasing circuit size significantly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithographic methods are used to construct devices, then device size can be controlled accurately, but material deposition variability causes performance inconsistency
Solution Approach 1:
The patent segments the device fabrication process into two independent stages: (1) photolithographic patterning to define device geometry with high precision, and (2) separate material deposition processes for each device layer. This segmentation isolates the geometric precision advantage of photolithography from the material deposition variability, allowing each process to optimize its own parameters without compounding errors.
Solution Approach 2:
The patent performs preliminary characterization and mapping of material deposition variability across the wafer surface before device fabrication. This preliminary action creates a deposition map that is used to adjust device parameters or select optimal locations, compensating for anticipated material variability before it affects device performance.
2Reliability
If large-size precision resistors are used, then accuracy within 0.005% is achieved, but area consumption increases significantly
Solution Approach 1:
The patent changes the material parameters and deposition conditions to achieve higher precision in smaller device geometries. By optimizing material composition, deposition temperature, and layer structure, the patent enables sub-micron resistors to achieve precision levels previously only attainable with millimeter-scale devices, thus reducing area consumption while maintaining accuracy.
Solution Approach 2:
The patent uses photolithographic patterning to create precise geometric copies of resistor structures at reduced scales. The patterning process replicates the geometric design with high fidelity, and when combined with controlled material deposition, produces small resistors that inherit the precision of the pattern while occupying minimal area.
3Ease of manufacture
If material deposition is performed by sputtering or vapor deposition, then device structure is formed, but significant attribute variability occurs
Solution Approach 1:
The patent implements feedback control in the material deposition process by continuously monitoring deposition rate, film thickness, and material properties in real-time. Sensors detect variations during deposition, and the system automatically adjusts deposition parameters to maintain consistency, thereby reducing attribute variability while preserving the ease of manufacture provided by sputtering and vapor deposition techniques.
Data Source
AI summary
A device source wafer includes a wafer substrate, devices formed on or in the wafer substrate at a location on the wafer substrate, and test structures disposed on the wafer substrate connected to some but not all of the devices. The devices include a first device disposed at a first location and a second device disposed at a second different location on the wafer substrate. The test structures include at least a first test structure connected to the first device and a second test structure connected to the second device. The first test structure is adapted to measuring a characteristic of the first device and the second test structure is adapted to measuring the characteristic of the second device. An estimated characteristic of unmeasured devices is derived from the first and second device locations and measured characteristics and the device is selected based on the estimated characteristic.