Transfer-Printed On-Chip Inductors for High-Q RF Integration
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Solution Overview
Problem
Integrated inductors on-chip typically have lower quality factors compared to surface mounted devices, limiting their performance in RF applications such as Low Noise Amplifiers and Power Amplifiers.
Innovation Solution
The integration of a micro-transfer printed inductor with a dielectric layer comprising cobalt nanoparticles on a silicon-on-insulator wafer, which maintains high quality factor and is compatible with semiconductor processes by forming the inductor separately on a native substrate and transferring it onto the target wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If inductors are integrated directly on-chip, then device integration is improved, but quality factor deteriorates
Solution Approach 1:
The inductor fabrication process is segmented into two independent stages: first forming the inductor structure on a separate native substrate, then transferring it to the target semiconductor wafer. This segmentation allows each stage to be optimized independently, achieving both high integration and high quality factor
Solution Approach 2:
A transfer substrate acts as an intermediary between the inductor fabrication process and the final chip integration. The native substrate serves as a temporary platform that enables precise inductor formation and subsequent transfer to the target wafer, resolving the conflict between integration and performance
2Reliability
If surface mounted devices are used, then quality factor is improved, but device integration deteriorates
Solution Approach 1:
The inductor is fabricated as a separate entity on a native substrate with optimized geometry and materials for high Q-factor, then copied onto the target chip through transfer printing. This copying approach preserves the high performance characteristics while achieving on-chip integration
Solution Approach 2:
The solution moves the inductor fabrication to a different dimensional space (separate native substrate) before transferring to the chip plane. This dimensional transition enables independent optimization of inductor geometry for high Q-factor while maintaining integration benefits
3Ease of manufacture
If conventional inductor structures are used, then manufacturing simplicity is improved, but parasitic resistance increases
Solution Approach 1:
The inductor employs composite material structures including high-permeability magnetic cores and optimized conductor geometries formed on the native substrate. These composite structures reduce parasitic resistance through enhanced magnetic coupling and current distribution while maintaining manufacturability through standard deposition and patterning processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides high quality factor inductors with reduced parasitic resistance and higher self-resonating frequency, enhancing the performance of RF components like LNAs and PAs by minimizing noise and loss.
Implementation Method 1
a dielectric layer with a relative permittivity of about three (µr≈3)
Data Source
AI summary
A method of forming a semiconductor structure including forming an inductor on a substrate and forming one or more semiconductor devices in a semiconductor wafer. The method further includes transferring the inductor from the substrate onto the semiconductor wafer, and forming a redistribution layer electrically connecting the inductor to at least one of the one or more semiconductor devices.